Triple
T8284547
| Position | Surface form | Disambiguated ID | Type / Status |
|---|---|---|---|
| Subject | Microprocessor without Interlocked Pipeline Stages |
E193757
|
entity |
| Predicate | hasVariant |
P455
|
FINISHED |
| Object |
MIPS II
MIPS II is the second-generation version of the MIPS instruction set architecture, extending the original design with additional instructions and features for improved performance and functionality.
|
E724103
|
NE FINISHED |
Provenance (5 batches)
| Stage | Batch ID | Job type | Status |
|---|---|---|---|
| creating | batch_69ca82e217a48190880695635c44b2ed |
elicitation | completed |
| NER | batch_69cb7ad0535081908bb234cfc0e32b32 |
ner | completed |
| NED1 | batch_69cd687e64a08190a45a1cf5f5c32291 |
ned_source_triple | completed |
| NED2 | batch_69cd7e2bdae08190adc51e904e85695e |
ned_description | completed |
| NEDg | batch_69cd6d55196881909cf5ec925792e09f |
nedg | completed |
Created at: March 30, 2026, 5:52 p.m.