Triple
T986386
| Position | Surface form | Disambiguated ID | Type / Status |
|---|---|---|---|
| Subject | SGI |
E21289
|
entity |
| Predicate | processorArchitecture |
P8609
|
FINISHED |
| Object | MIPS |
E37330
|
NE FINISHED |
How this triple was built (3 steps)
Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.
NER
Named-entity recognition
gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: MIPS | Statement: [SGI, processorArchitecture, MIPS]
NED1
Entity disambiguation (via context triple)
gpt-5-mini-2025-08-07
Target entity: MIPS Context triple: [SGI, processorArchitecture, MIPS]
-
A.
MIPS
chosen
MIPS is a RISC (Reduced Instruction Set Computer) processor architecture widely used in embedded systems, networking equipment, and academic settings.
-
B.
SPIM
SPIM was the former ICAO airport code for Jorge Chávez International Airport in Lima, Peru, before it was changed to SPJC.
-
C.
SPARC microprocessor architecture
The SPARC microprocessor architecture is a RISC-based instruction set architecture widely used in high-performance and enterprise servers, originally created to power scalable, multi-processor systems.
-
D.
RISC-V
RISC-V is an open, extensible instruction set architecture (ISA) based on the reduced instruction set computing (RISC) principles, widely used for research, embedded systems, and increasingly general-purpose computing.
-
E.
Acorn RISC Machine
Acorn RISC Machine (ARM) is a family of energy-efficient reduced instruction set computer (RISC) architectures widely used in mobile devices, embedded systems, and increasingly in servers and personal computers.
- F. None of above.
- G. Unsure - the case is ambiguous/there is not enough information to decide.
PD
Predicate disambiguation
gpt-5-mini-2025-08-07
Target predicate: processorArchitecture Context triple: [SGI, processorArchitecture, MIPS]
-
A.
cpuArchitecture
chosen
Indicates the type of processor instruction set or hardware architecture that a computing system or component is designed to run on.
-
B.
graphicsArchitecture
Indicates the underlying design or structural framework that defines how a system’s graphics or visual rendering components are organized and operate.
-
C.
cpu
Indicates that an entity functions as, contains, or is associated with a central processing unit (CPU) in a computational system.
-
D.
cpuCoreMicroarchitecture
Indicates the specific microarchitecture design implemented in a given CPU core.
-
E.
cpuFamily
Indicates that one CPU belongs to, or is categorized under, a particular CPU family or architecture lineage.
- F. None of above.
Provenance (4 batches)
The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.
| Step | Stage | Batch ID | Status | When |
|---|---|---|---|---|
| creating | Elicitation | batch_69a493c383dc8190a03257f22d4b4183 |
completed | March 1, 2026, 7:30 p.m. |
| NER | Named-entity recognition | batch_69a4b496b7308190a9c201244330b784 |
completed | March 1, 2026, 9:50 p.m. |
| NED1 | Entity disambiguation (via context triple) | batch_69ac1ce5c0d48190ab023cec30b2c25a |
completed | March 7, 2026, 12:41 p.m. |
| PD | Predicate disambiguation | batch_69a4b2abccbc8190a83af432f89eacf5 |
completed | March 1, 2026, 9:42 p.m. |
Created at: March 1, 2026, 7:41 p.m.