Triple

Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).

Phrase: Cadence SMV | Statement: [Symbolic Model Checking, usedInTool, Cadence SMV]

Target entity: Cadence SMV
Context triple: [Symbolic Model Checking, usedInTool, Cadence SMV]

• A. SystemVerilog
  SystemVerilog is a hardware description and verification language widely used to design, model, and verify complex digital integrated circuits and systems.
• B. Verilog
  Verilog is a hardware description language (HDL) used to model, design, and verify digital circuits and systems such as those implemented in CPLDs and FPGAs.
• C. Bluespec SystemVerilog
  Bluespec SystemVerilog is a high-level hardware description language that extends Verilog with rule-based, functional programming concepts to enable more abstract and formally verifiable hardware design.
• D. ModelSim
  ModelSim is a widely used hardware description language (HDL) simulation and debugging environment for VHDL, Verilog, and SystemVerilog designs.
• E. IEEE 1364
  IEEE 1364 is the IEEE standard that defines the Verilog hardware description language used for modeling and designing digital electronic systems.
• F. None of above. chosen
• G. Unsure - the case is ambiguous/there is not enough information to decide.

Generate a one-sentence description of the target entity. 
You are given a context triple in the form (subject, predicate, object), where the object is the target entity. 
# Instructions
Use the triple to infer relevant information about the entity. Describe the entity based on what is most defining, well-known. 
Avoid repeating the information from the triple, unless really essential.
# Response Format
Return only the sentence: "Description: [one-sentence description of the target entity]"

Entity: Cadence SMV
Triple: [Symbolic Model Checking, usedInTool, Cadence SMV]

Cadence SMV is a formal verification tool that uses symbolic model checking techniques to automatically verify hardware and protocol designs against temporal logic specifications.

Target entity: Cadence SMV
Target entity description: Cadence SMV is a formal verification tool that uses symbolic model checking techniques to automatically verify hardware and protocol designs against temporal logic specifications.

• A. SystemVerilog
  SystemVerilog is a hardware description and verification language widely used to design, model, and verify complex digital integrated circuits and systems.
• B. Verilog
  Verilog is a hardware description language (HDL) used to model, design, and verify digital circuits and systems such as those implemented in CPLDs and FPGAs.
• C. Bluespec SystemVerilog
  Bluespec SystemVerilog is a high-level hardware description language that extends Verilog with rule-based, functional programming concepts to enable more abstract and formally verifiable hardware design.
• D. ModelSim
  ModelSim is a widely used hardware description language (HDL) simulation and debugging environment for VHDL, Verilog, and SystemVerilog designs.
• E. IEEE 1364
  IEEE 1364 is the IEEE standard that defines the Verilog hardware description language used for modeling and designing digital electronic systems.
• F. None of above. chosen