Cadence SMV
E824081
Cadence SMV is a formal verification tool that uses symbolic model checking techniques to automatically verify hardware and protocol designs against temporal logic specifications.
Statements (40)
| Predicate | Object |
|---|---|
| instanceOf |
formal verification tool
ⓘ
hardware verification tool ⓘ symbolic model checker ⓘ |
| appliedIn |
digital circuit verification
ⓘ
hardware design verification ⓘ protocol verification ⓘ |
| basedOn | model checking ⓘ |
| canDetect |
design errors
ⓘ
protocol violations ⓘ |
| canProve | correctness of temporal properties ⓘ |
| checksAgainst | temporal logic specifications ⓘ |
| developedFor | industrial-scale verification ⓘ |
| domain |
electronic design automation
ⓘ
formal methods ⓘ |
| hasFeature |
counterexample generation
ⓘ
modeling language for finite-state systems ⓘ property specification language ⓘ symbolic reachability analysis ⓘ |
| implements | symbolic model checking algorithms ⓘ |
| input |
finite-state models
ⓘ
temporal logic formulas ⓘ |
| output |
counterexamples for violated properties
ⓘ
verification results ⓘ |
| performs | automatic verification ⓘ |
| relatedTo |
NuSMV
NERFINISHED
ⓘ
SMV NERFINISHED ⓘ |
| supports |
assertion-based verification
ⓘ
liveness property verification ⓘ property checking ⓘ safety property verification ⓘ |
| supportsLogic |
CTL
NERFINISHED
ⓘ
LTL ⓘ temporal logic ⓘ |
| usedBy |
formal verification specialists
ⓘ
hardware verification engineers ⓘ |
| usesDataStructure | binary decision diagrams ⓘ |
| usesRepresentation | symbolic state space representation ⓘ |
| usesTechnique | symbolic model checking ⓘ |
| verifies |
hardware designs
ⓘ
protocol designs ⓘ |
Referenced by (1)
Full triples — surface form annotated when it differs from this entity's canonical label.