Triple

T8284639
Position Surface form Disambiguated ID Type / Status
Subject CP1 floating-point coprocessor E193759 entity
Predicate alsoKnownAs P39 FINISHED
Object MIPS floating-point unit E193759 NE FINISHED

How this triple was built (2 steps)

Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.

NER Named-entity recognition gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: MIPS floating-point unit | Statement: [CP1 floating-point coprocessor, alsoKnownAs, MIPS floating-point unit]
NED1 Entity disambiguation (via context triple) gpt-5-mini-2025-08-07 
Target entity: MIPS floating-point unit
Context triple: [CP1 floating-point coprocessor, alsoKnownAs, MIPS floating-point unit]
  • A. MIPS
    MIPS is a RISC (Reduced Instruction Set Computer) processor architecture widely used in embedded systems, networking equipment, and academic settings.
  • B. CP1 floating-point coprocessor chosen
    The CP1 floating-point coprocessor is a dedicated hardware unit used in MIPS architectures to perform floating-point arithmetic operations efficiently.
  • C. MIPS R5000
    The MIPS R5000 is a 64-bit RISC microprocessor from the MIPS family, widely used in mid-1990s workstations and embedded systems for its balance of performance and cost.
  • D. MIPS R4600
    The MIPS R4600 is a 64-bit RISC microprocessor from the MIPS family, widely used in mid-1990s workstations and embedded systems for its balance of performance and cost.
  • E. SPARC microprocessor architecture
    The SPARC microprocessor architecture is a RISC-based instruction set architecture widely used in high-performance and enterprise servers, originally created to power scalable, multi-processor systems.
  • F. None of above.
  • G. Unsure - the case is ambiguous/there is not enough information to decide.

Provenance (3 batches)

The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.

Step Stage Batch ID Status When
creating Elicitation batch_69ca82e217a48190880695635c44b2ed completed March 30, 2026, 2:04 p.m.
NER Named-entity recognition batch_69cb7ad0535081908bb234cfc0e32b32 completed March 31, 2026, 7:42 a.m.
NED1 Entity disambiguation (via context triple) batch_69cd687e64a08190a45a1cf5f5c32291 completed April 1, 2026, 6:48 p.m.
Created at: March 30, 2026, 5:52 p.m.