Triple

T8284582

Position	Surface form	Disambiguated ID	Type / Status
Subject	Microprocessor without Interlocked Pipeline Stages	`E193757`	entity
Predicate	hasExtension	`P455`	FINISHED
Object	MIPS MT (multithreading) MIPS MT (multithreading) is a hardware multithreading extension to the MIPS architecture that allows multiple threads to share a single processor core for improved throughput and latency hiding.	`E37330`	NE FINISHED

How this triple was built (4 steps)

Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.

NER Named-entity recognition gpt-5-mini

Instruction

Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).

Input

Phrase: MIPS MT (multithreading) | Statement: [Microprocessor without Interlocked Pipeline Stages, hasExtension, MIPS MT (multithreading)]

NED1 Entity disambiguation (via context triple) gpt-5-mini-2025-08-07

Target entity: MIPS MT (multithreading)
Context triple: [Microprocessor without Interlocked Pipeline Stages, hasExtension, MIPS MT (multithreading)]

A. MIPS
MIPS is a RISC (Reduced Instruction Set Computer) processor architecture widely used in embedded systems, networking equipment, and academic settings.
B. MIPS R5000
The MIPS R5000 is a 64-bit RISC microprocessor from the MIPS family, widely used in mid-1990s workstations and embedded systems for its balance of performance and cost.
C. MIPS R4600
The MIPS R4600 is a 64-bit RISC microprocessor from the MIPS family, widely used in mid-1990s workstations and embedded systems for its balance of performance and cost.
D. "How to Make a Multiprocessor Computer That Correctly Executes Multiprocess Programs"
"How to Make a Multiprocessor Computer That Correctly Executes Multiprocess Programs" is a seminal paper by Leslie Lamport that introduced foundational concepts for ensuring correctness and consistency in concurrent and multiprocessor systems.
E. Intel Hyper-Threading Technology
Intel Hyper-Threading Technology is Intel’s simultaneous multithreading implementation that allows a single physical processor core to appear as multiple logical cores to improve parallel processing and overall performance.
F. None of above. chosen
G. Unsure - the case is ambiguous/there is not enough information to decide.

NEDg Description generation gpt-5.1

Instruction

Generate a one-sentence description of the target entity. 
You are given a context triple in the form (subject, predicate, object), where the object is the target entity. 
# Instructions
Use the triple to infer relevant information about the entity. Describe the entity based on what is most defining, well-known. 
Avoid repeating the information from the triple, unless really essential.
# Response Format
Return only the sentence: "Description: [one-sentence description of the target entity]"

Input

Entity: MIPS MT (multithreading)
Triple: [Microprocessor without Interlocked Pipeline Stages, hasExtension, MIPS MT (multithreading)]

Generated description

MIPS MT (multithreading) is a hardware multithreading extension to the MIPS architecture that allows multiple threads to share a single processor core for improved throughput and latency hiding.

NED2 Entity disambiguation (via description) gpt-5-mini-2025-08-07

Target entity: MIPS MT (multithreading)
Target entity description: MIPS MT (multithreading) is a hardware multithreading extension to the MIPS architecture that allows multiple threads to share a single processor core for improved throughput and latency hiding.

A. MIPS chosen
MIPS is a RISC (Reduced Instruction Set Computer) processor architecture widely used in embedded systems, networking equipment, and academic settings.
B. MIPS R5000
The MIPS R5000 is a 64-bit RISC microprocessor from the MIPS family, widely used in mid-1990s workstations and embedded systems for its balance of performance and cost.
C. MIPS R4600
The MIPS R4600 is a 64-bit RISC microprocessor from the MIPS family, widely used in mid-1990s workstations and embedded systems for its balance of performance and cost.
D. "How to Make a Multiprocessor Computer That Correctly Executes Multiprocess Programs"
"How to Make a Multiprocessor Computer That Correctly Executes Multiprocess Programs" is a seminal paper by Leslie Lamport that introduced foundational concepts for ensuring correctness and consistency in concurrent and multiprocessor systems.
E. Intel Hyper-Threading Technology
Intel Hyper-Threading Technology is Intel’s simultaneous multithreading implementation that allows a single physical processor core to appear as multiple logical cores to improve parallel processing and overall performance.
F. None of above.

Provenance (5 batches)

The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.

Step	Stage	Batch ID	Status	When
creating	Elicitation	`batch_69ca82e217a48190880695635c44b2ed`	completed	March 30, 2026, 2:04 p.m.
NER	Named-entity recognition	`batch_69cb7ad0535081908bb234cfc0e32b32`	completed	March 31, 2026, 7:42 a.m.
NED1	Entity disambiguation (via context triple)	`batch_69cd687e64a08190a45a1cf5f5c32291`	completed	April 1, 2026, 6:48 p.m.
NEDg	Description generation	`batch_69cd6d55196881909cf5ec925792e09f`	completed	April 1, 2026, 7:09 p.m.
NED2	Entity disambiguation (via description)	`batch_69cd7e2bdae08190adc51e904e85695e`	completed	April 1, 2026, 8:21 p.m.

Created at: March 30, 2026, 5:52 p.m.