Triple

T8284431
Position Surface form Disambiguated ID Type / Status
Subject QEMU RISC-V target E193755 entity
Predicate supportsISAExtension P74581 FINISHED
Object RISC-V I base integer extension
The RISC-V I base integer extension is the fundamental 32-bit integer instruction set that forms the core of the RISC-V architecture, providing essential arithmetic, logical, control-flow, and memory access operations.
E37329 NE FINISHED

How this triple was built (5 steps)

Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.

NER Named-entity recognition gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: RISC-V I base integer extension | Statement: [QEMU RISC-V target, supportsISAExtension, RISC-V I base integer extension]
NED1 Entity disambiguation (via context triple) gpt-5-mini-2025-08-07
Target entity: RISC-V I base integer extension
Context triple: [QEMU RISC-V target, supportsISAExtension, RISC-V I base integer extension]
  • A. RISC-V
    RISC-V is an open, extensible instruction set architecture (ISA) based on the reduced instruction set computing (RISC) principles, widely used for research, embedded systems, and increasingly general-purpose computing.
  • B. Spike RISC-V ISA simulator
    Spike RISC-V ISA simulator is the official reference software simulator for the RISC-V instruction set architecture, used to validate and test RISC-V implementations.
  • C. RISC I
    RISC I is an early experimental reduced instruction set computer (RISC) processor design developed at UC Berkeley that helped pioneer and popularize the RISC architecture approach.
  • D. RISC-V International
    RISC-V International is the global nonprofit consortium that oversees the development, standardization, and promotion of the open RISC-V instruction set architecture.
  • E. MIPS
    MIPS is a RISC (Reduced Instruction Set Computer) processor architecture widely used in embedded systems, networking equipment, and academic settings.
  • F. None of above. chosen
  • G. Unsure - the case is ambiguous/there is not enough information to decide.
NEDg Description generation gpt-5.1
Instruction
Generate a one-sentence description of the target entity. 
You are given a context triple in the form (subject, predicate, object), where the object is the target entity. 
# Instructions
Use the triple to infer relevant information about the entity. Describe the entity based on what is most defining, well-known. 
Avoid repeating the information from the triple, unless really essential.
# Response Format
Return only the sentence: "Description: [one-sentence description of the target entity]"
Input
Entity: RISC-V I base integer extension
Triple: [QEMU RISC-V target, supportsISAExtension, RISC-V I base integer extension]
Generated description
The RISC-V I base integer extension is the fundamental 32-bit integer instruction set that forms the core of the RISC-V architecture, providing essential arithmetic, logical, control-flow, and memory access operations.
NED2 Entity disambiguation (via description) gpt-5-mini-2025-08-07
Target entity: RISC-V I base integer extension
Target entity description: The RISC-V I base integer extension is the fundamental 32-bit integer instruction set that forms the core of the RISC-V architecture, providing essential arithmetic, logical, control-flow, and memory access operations.
  • A. RISC-V chosen
    RISC-V is an open, extensible instruction set architecture (ISA) based on the reduced instruction set computing (RISC) principles, widely used for research, embedded systems, and increasingly general-purpose computing.
  • B. Spike RISC-V ISA simulator
    Spike RISC-V ISA simulator is the official reference software simulator for the RISC-V instruction set architecture, used to validate and test RISC-V implementations.
  • C. RISC I
    RISC I is an early experimental reduced instruction set computer (RISC) processor design developed at UC Berkeley that helped pioneer and popularize the RISC architecture approach.
  • D. RISC-V International
    RISC-V International is the global nonprofit consortium that oversees the development, standardization, and promotion of the open RISC-V instruction set architecture.
  • E. MIPS
    MIPS is a RISC (Reduced Instruction Set Computer) processor architecture widely used in embedded systems, networking equipment, and academic settings.
  • F. None of above.
PD Predicate disambiguation gpt-5-mini-2025-08-07
Target predicate: supportsISAExtension
Context triple: [QEMU RISC-V target, supportsISAExtension, RISC-V I base integer extension]
  • A. hasBaseISA
    Indicates that an entity’s base or fundamental type is a specified ISA (Instruction Set Architecture) or foundational classification.
  • B. instructionSetExtensions chosen
    Indicates that one entity defines, supports, or includes additional instruction set features or extensions relative to another.
  • C. hasInstructionSet
    Indicates that one entity (typically a processor or system) is defined as using or supporting a particular instruction set.
  • D. supportsExtensionModel
    Indicates that one entity provides compatibility or functionality for using a specified extension model associated with another entity.
  • E. hasFeature
    Indicates that an entity possesses, exhibits, or includes a particular characteristic, attribute, or component.
  • F. None of above.

Provenance (6 batches)

The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.

Step Stage Batch ID Status When
creating Elicitation batch_69ca82e217a48190880695635c44b2ed completed March 30, 2026, 2:04 p.m.
NER Named-entity recognition batch_69cb7ad0535081908bb234cfc0e32b32 completed March 31, 2026, 7:42 a.m.
NED1 Entity disambiguation (via context triple) batch_69cd952399dc8190914951d4e9e36c38 completed April 1, 2026, 9:58 p.m.
NEDg Description generation batch_69cdab59ac188190ac017651b5a9a04a completed April 1, 2026, 11:33 p.m.
NED2 Entity disambiguation (via description) batch_69cdb2ae376c8190b3918ba6b269dba9 completed April 2, 2026, 12:05 a.m.
PD Predicate disambiguation batch_69cb70ad9fc081908741f8c4a4141edf completed March 31, 2026, 6:58 a.m.
Created at: March 30, 2026, 5:52 p.m.