Triple

T8283995
Position Surface form Disambiguated ID Type / Status
Subject Berkeley RISC projects E193746 entity
Predicate notableWork P4 FINISHED
Object RISC I microprocessor E339011 NE FINISHED

How this triple was built (2 steps)

Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.

NER Named-entity recognition gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: RISC I microprocessor | Statement: [Berkeley RISC projects, notableWork, RISC I microprocessor]
NED1 Entity disambiguation (via context triple) gpt-5-mini-2025-08-07 
Target entity: RISC I microprocessor
Context triple: [Berkeley RISC projects, notableWork, RISC I microprocessor]
  • A. RCA 1802 microprocessor
    The RCA 1802 microprocessor is an early CMOS-based 8-bit CPU notable for its low power consumption, radiation hardness, and use in spacecraft and embedded systems in the 1970s and 1980s.
  • B. Motorola 6800 microprocessor
    The Motorola 6800 microprocessor is an 8-bit CPU introduced in the mid-1970s that became influential in early microcomputer and embedded system designs.
  • C. Zilog Z8000 microprocessor
    The Zilog Z8000 microprocessor is a 16-bit CPU introduced in the late 1970s, notable for its advanced architecture and use in early workstations and embedded systems.
  • D. RISC I chosen
    RISC I is an early experimental reduced instruction set computer (RISC) processor design developed at UC Berkeley that helped pioneer and popularize the RISC architecture approach.
  • E. Risc PC
    Risc PC is a modular personal computer introduced by Acorn Computers in the 1990s, known for its RISC-based architecture and expandability.
  • F. None of above.
  • G. Unsure - the case is ambiguous/there is not enough information to decide.

Provenance (3 batches)

The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.

Step Stage Batch ID Status When
creating Elicitation batch_69ca82e217a48190880695635c44b2ed completed March 30, 2026, 2:04 p.m.
NER Named-entity recognition batch_69cb7ad0535081908bb234cfc0e32b32 completed March 31, 2026, 7:42 a.m.
NED1 Entity disambiguation (via context triple) batch_69cd687e64a08190a45a1cf5f5c32291 completed April 1, 2026, 6:48 p.m.
Created at: March 30, 2026, 5:52 p.m.