Triple
T8249523
| Position | Surface form | Disambiguated ID | Type / Status |
|---|---|---|---|
| Subject | RISC-V International |
E192921
|
entity |
| Predicate | coordinates |
P1076
|
FINISHED |
| Object |
RISC-V technical working groups
RISC-V technical working groups are specialized committees of experts that collaboratively define, develop, and maintain the open RISC-V instruction set architecture and its related standards.
|
E192921
|
NE FINISHED |
How this triple was built (4 steps)
Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.
NER
Named-entity recognition
gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: RISC-V technical working groups | Statement: [RISC-V International, coordinates, RISC-V technical working groups]
NED1
Entity disambiguation (via context triple)
gpt-5-mini-2025-08-07
Target entity: RISC-V technical working groups Context triple: [RISC-V International, coordinates, RISC-V technical working groups]
-
A.
RISC-V International
RISC-V International is the global nonprofit consortium that oversees the development, standardization, and promotion of the open RISC-V instruction set architecture.
-
B.
RISC-V
RISC-V is an open, extensible instruction set architecture (ISA) based on the reduced instruction set computing (RISC) principles, widely used for research, embedded systems, and increasingly general-purpose computing.
-
C.
Spike RISC-V ISA simulator
Spike RISC-V ISA simulator is the official reference software simulator for the RISC-V instruction set architecture, used to validate and test RISC-V implementations.
-
D.
SiFive
SiFive is a semiconductor company known for designing customizable RISC‑V processor cores and platforms used in a wide range of computing applications.
-
E.
Bytecode Alliance
Bytecode Alliance is a nonprofit industry consortium focused on advancing secure, modular, and portable software through technologies built around WebAssembly.
- F. None of above. chosen
- G. Unsure - the case is ambiguous/there is not enough information to decide.
NEDg
Description generation
gpt-5.1
Instruction
Generate a one-sentence description of the target entity. You are given a context triple in the form (subject, predicate, object), where the object is the target entity. # Instructions Use the triple to infer relevant information about the entity. Describe the entity based on what is most defining, well-known. Avoid repeating the information from the triple, unless really essential. # Response Format Return only the sentence: "Description: [one-sentence description of the target entity]"
Input
Entity: RISC-V technical working groups Triple: [RISC-V International, coordinates, RISC-V technical working groups]
Generated description
RISC-V technical working groups are specialized committees of experts that collaboratively define, develop, and maintain the open RISC-V instruction set architecture and its related standards.
NED2
Entity disambiguation (via description)
gpt-5-mini-2025-08-07
Target entity: RISC-V technical working groups Target entity description: RISC-V technical working groups are specialized committees of experts that collaboratively define, develop, and maintain the open RISC-V instruction set architecture and its related standards.
-
A.
RISC-V International
chosen
RISC-V International is the global nonprofit consortium that oversees the development, standardization, and promotion of the open RISC-V instruction set architecture.
-
B.
RISC-V
RISC-V is an open, extensible instruction set architecture (ISA) based on the reduced instruction set computing (RISC) principles, widely used for research, embedded systems, and increasingly general-purpose computing.
-
C.
Spike RISC-V ISA simulator
Spike RISC-V ISA simulator is the official reference software simulator for the RISC-V instruction set architecture, used to validate and test RISC-V implementations.
-
D.
SiFive
SiFive is a semiconductor company known for designing customizable RISC‑V processor cores and platforms used in a wide range of computing applications.
-
E.
Bytecode Alliance
Bytecode Alliance is a nonprofit industry consortium focused on advancing secure, modular, and portable software through technologies built around WebAssembly.
- F. None of above.
Provenance (5 batches)
The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.
| Step | Stage | Batch ID | Status | When |
|---|---|---|---|---|
| creating | Elicitation | batch_69ca82de7b8c81908d8106f8a53cff9b |
completed | March 30, 2026, 2:04 p.m. |
| NER | Named-entity recognition | batch_69cb78c817708190ad1c364e12083d26 |
completed | March 31, 2026, 7:33 a.m. |
| NED1 | Entity disambiguation (via context triple) | batch_69cd353888208190941d1c0b7b911cdd |
completed | April 1, 2026, 3:09 p.m. |
| NEDg | Description generation | batch_69cd37a71af481909e82aa29ae558c4a |
completed | April 1, 2026, 3:20 p.m. |
| NED2 | Entity disambiguation (via description) | batch_69cd4ef034ec8190a4229b21e6088c79 |
completed | April 1, 2026, 4:59 p.m. |
Created at: March 30, 2026, 5:48 p.m.