Triple
T7032642
| Position | Surface form | Disambiguated ID | Type / Status |
|---|---|---|---|
| Subject | Bonnell |
E163305
|
entity |
| Predicate | floatingPointUnit |
P28922
|
FINISHED |
| Object | x87 FPU |
E637383
|
NE FINISHED |
How this triple was built (2 steps)
Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.
NER
Named-entity recognition
gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: x87 FPU | Statement: [Bonnell, floatingPointUnit, x87 FPU]
NED1
Entity disambiguation (via context triple)
gpt-5-mini-2025-08-07
Target entity: x87 FPU Context triple: [Bonnell, floatingPointUnit, x87 FPU]
-
A.
x87 FPU
chosen
The x87 FPU is the dedicated floating-point coprocessor architecture used in IA-32 processors to perform hardware-accelerated arithmetic on real and complex numbers.
-
B.
x86
x86 is a widely used family of backward-compatible instruction set architectures for computer processors, originally developed by Intel and forming the basis of most desktop and laptop CPUs.
-
C.
VFP floating-point extension
The VFP floating-point extension is an ARM architecture coprocessor feature that provides hardware support for high-performance single- and double-precision floating-point arithmetic.
-
D.
CP1 floating-point coprocessor
The CP1 floating-point coprocessor is a dedicated hardware unit used in MIPS architectures to perform floating-point arithmetic operations efficiently.
-
E.
Intel i860
The Intel i860 was a high-performance RISC microprocessor from the late 1980s and early 1990s, notable for its VLIW-like architecture and integrated floating-point and graphics capabilities aimed at workstations and supercomputers.
- F. None of above.
- G. Unsure - the case is ambiguous/there is not enough information to decide.
Provenance (3 batches)
The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.
| Step | Stage | Batch ID | Status | When |
|---|---|---|---|---|
| creating | Elicitation | batch_69c6885d691c81908cf7d31083113886 |
completed | March 27, 2026, 1:38 p.m. |
| NER | Named-entity recognition | batch_69c6e77415e88190ab65137382f1b155 |
completed | March 27, 2026, 8:24 p.m. |
| NED1 | Entity disambiguation (via context triple) | batch_69c7885d83d4819099cc334dd2841f3b |
completed | March 28, 2026, 7:50 a.m. |
Created at: March 27, 2026, 2:36 p.m.