Triple
T3518552
| Position | Surface form | Disambiguated ID | Type / Status |
|---|---|---|---|
| Subject | VLSI technology |
E74364
|
entity |
| Predicate | usesLanguage |
P238
|
FINISHED |
| Object |
SystemVerilog
SystemVerilog is a hardware description and verification language widely used to design, model, and verify complex digital integrated circuits and systems.
|
E365872
|
NE FINISHED |
Provenance (5 batches)
| Stage | Batch ID | Job type | Status |
|---|---|---|---|
| creating | batch_69ad85cfb5c881909c9a2edd9d6043cc |
elicitation | completed |
| NER | batch_69adbc49dea88190924c8abd29aabdad |
ner | completed |
| NED1 | batch_69b37e80cd588190ae012f151ef59c52 |
ned_source_triple | completed |
| NED2 | batch_69b382b43b708190be7ae3d44b0a393a |
ned_description | completed |
| NEDg | batch_69b37ef902208190842ddbe6427ca42b |
nedg | completed |
Created at: March 8, 2026, 3:19 p.m.