Triple

Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).

Phrase: SystemVerilog | Statement: [VLSI technology, usesLanguage, SystemVerilog]

Target entity: SystemVerilog
Context triple: [VLSI technology, usesLanguage, SystemVerilog]

• A. Verilog
  Verilog is a hardware description language (HDL) used to model, design, and verify digital circuits and systems such as those implemented in CPLDs and FPGAs.
• B. VHDL
  VHDL is a hardware description language used to model, simulate, and implement digital electronic systems such as FPGAs and CPLDs.
• C. SVA
  SVA is the ICAO airline designator used to identify Saudia, the flag carrier airline of Saudi Arabia, in international aviation operations.
• D. RISC-V
  RISC-V is an open, extensible instruction set architecture (ISA) based on the reduced instruction set computing (RISC) principles, widely used for research, embedded systems, and increasingly general-purpose computing.
• E. Spike RISC-V ISA simulator
  Spike RISC-V ISA simulator is the official reference software simulator for the RISC-V instruction set architecture, used to validate and test RISC-V implementations.
• F. None of above. chosen
• G. Unsure - the case is ambiguous/there is not enough information to decide.

Generate a one-sentence description of the target entity. 
You are given a context triple in the form (subject, predicate, object), where the object is the target entity. 
# Instructions
Use the triple to infer relevant information about the entity. Describe the entity based on what is most defining, well-known. 
Avoid repeating the information from the triple, unless really essential.
# Response Format
Return only the sentence: "Description: [one-sentence description of the target entity]"

Entity: SystemVerilog
Triple: [VLSI technology, usesLanguage, SystemVerilog]

SystemVerilog is a hardware description and verification language widely used to design, model, and verify complex digital integrated circuits and systems.

Target entity: SystemVerilog
Target entity description: SystemVerilog is a hardware description and verification language widely used to design, model, and verify complex digital integrated circuits and systems.

• A. Verilog
  Verilog is a hardware description language (HDL) used to model, design, and verify digital circuits and systems such as those implemented in CPLDs and FPGAs.
• B. VHDL
  VHDL is a hardware description language used to model, simulate, and implement digital electronic systems such as FPGAs and CPLDs.
• C. SVA
  SVA is the ICAO airline designator used to identify Saudia, the flag carrier airline of Saudi Arabia, in international aviation operations.
• D. RISC-V
  RISC-V is an open, extensible instruction set architecture (ISA) based on the reduced instruction set computing (RISC) principles, widely used for research, embedded systems, and increasingly general-purpose computing.
• E. Spike RISC-V ISA simulator
  Spike RISC-V ISA simulator is the official reference software simulator for the RISC-V instruction set architecture, used to validate and test RISC-V implementations.
• F. None of above. chosen