Triple
T31733233
| Position | Surface form | Disambiguated ID | Type / Status |
|---|---|---|---|
| Subject | Design of ion-implanted MOSFET’s with very small physical dimensions |
E809917
|
entity |
| Predicate | instanceOf |
P0
|
FINISHED |
| Object | seminal work in microelectronics |
C13940
|
CONCEPT FINISHED |
How this triple was built (1 step)
Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.
CD
Concept disambiguation
gpt-5-mini-2025-08-07
Target class: seminal work in microelectronics Context triple: [Design of ion-implanted MOSFET’s with very small physical dimensions, instanceOf, seminal work in microelectronics]
-
A.
principle in microelectronics
A principle in microelectronics is a fundamental rule or concept that governs the behavior, design, and operation of electronic components and circuits at microscopic scales.
-
B.
microelectronics technology
chosen
Microelectronics technology is the field focused on designing, fabricating, and integrating extremely small electronic components and circuits—such as transistors, diodes, and integrated circuits—on semiconductor substrates to enable compact, high-performance electronic systems.
-
C.
integrated circuit technology
Integrated circuit technology is the design and fabrication of miniaturized electronic circuits on semiconductor chips, enabling complex, high-speed, and low-power electronic systems.
-
D.
foundational work in nanotechnology
Foundational work in nanotechnology encompasses the early theories, experiments, and techniques that established the principles for manipulating and engineering materials at the atomic and molecular scale.
-
E.
CMOS microprocessor
A CMOS microprocessor is a central processing unit implemented using complementary metal-oxide-semiconductor technology, providing high integration, low power consumption, and reliable digital computation on a single chip.
- F. None of above.
Provenance (1 batch)
The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.
| Step | Stage | Batch ID | Status | When |
|---|---|---|---|---|
| creating | Elicitation | batch_69f348e0e4908190a884582eca646fb7 |
completed | April 30, 2026, 12:19 p.m. |
Created at: April 30, 2026, 11:22 p.m.