Triple

T29938081
Position Surface form Disambiguated ID Type / Status
Subject GeForce3 E760422 entity
Predicate memoryClockRange P168347 FINISHED
Object approximately 400–550 MHz effective DDR depending on model LITERAL FINISHED

How this triple was built (2 steps)

Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.

NER Named-entity recognition gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: approximately 400–550 MHz effective DDR depending on model | Statement: [GeForce3, memoryClockRange, approximately 400–550 MHz effective DDR depending on model]
PD Predicate disambiguation gpt-5-mini-2025-08-07
Target predicate: memoryClockRange
Context triple: [GeForce3, memoryClockRange, approximately 400–550 MHz effective DDR depending on model]
  • A. memoryCycleTime
    Indicates the duration of a complete access cycle for a memory component or system.
  • B. minClockSpeed
    Indicates the minimum operating clock speed required or supported for a given hardware component or system.
  • C. clockSpeed
    Indicates the operating frequency at which a clock-driven component (such as a processor) performs its cycles or operations over time.
  • D. typicalRAMRange
    Indicates the usual or commonly expected range of RAM capacity associated with an entity.
  • E. ramSpeedMHz chosen
    Indicates the operating speed of a RAM module measured in megahertz (MHz).
  • F. None of above.

Provenance (3 batches)

The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.

Step Stage Batch ID Status When
creating Elicitation batch_69f22463f3648190a603c3ff305c660b completed April 29, 2026, 3:31 p.m.
NER Named-entity recognition batch_69f6b903538481909cffcb6cc1cc0e70 completed May 3, 2026, 2:54 a.m.
PD Predicate disambiguation batch_69f6b626120c819097c9ad04487570d7 completed May 3, 2026, 2:42 a.m.
Created at: April 29, 2026, 6:21 p.m.