Triple
T28610627
| Position | Surface form | Disambiguated ID | Type / Status |
|---|---|---|---|
| Subject | SH4 |
E724159
|
entity |
| Predicate | instanceOf |
P0
|
FINISHED |
| Object | SuperH architecture |
C54309
|
CONCEPT FINISHED |
How this triple was built (1 step)
Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.
CD
Concept disambiguation
gpt-5-mini-2025-08-07
Target class: SuperH architecture Context triple: [SH4, instanceOf, SuperH architecture]
-
A.
Super Nintendo Entertainment System enhancement chip
A Super Nintendo Entertainment System enhancement chip is a specialized coprocessor embedded in or alongside SNES game cartridges to extend the console’s native capabilities, such as graphics, sound, or processing power, for specific titles.
-
B.
Motorola 680x0 family processor
A Motorola 680x0 family processor is a 32-bit CISC microprocessor architecture used in many 1980s–1990s computers and workstations, known for its orthogonal instruction set and influential role in systems like the Apple Macintosh, Amiga, and Atari ST.
-
C.
Atari custom chip
An Atari custom chip is a specialized integrated circuit designed by Atari to handle specific tasks such as graphics, sound, or system control in their arcade and home console hardware, enhancing performance and capabilities beyond standard off-the-shelf components.
-
D.
Nintendo 64 hardware variant
A Nintendo 64 hardware variant is a specific version of the Nintendo 64 console distinguished by differences in physical design, internal components, regional specifications, or bundled features while remaining compatible with the same software library.
-
E.
Motorola 88000 family microprocessor
The Motorola 88000 family microprocessor is a series of 32-bit RISC CPUs developed by Motorola in the late 1980s, designed for high-performance computing and embedded systems with a clean, load-store architecture.
- F. None of above. chosen
Provenance (1 batch)
The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.
| Step | Stage | Batch ID | Status | When |
|---|---|---|---|---|
| creating | Elicitation | batch_69f01d816d7c8190a1fe27e3434041dc |
completed | April 28, 2026, 2:37 a.m. |
Created at: April 28, 2026, 4:29 a.m.