Triple
T20473397
| Position | Surface form | Disambiguated ID | Type / Status |
|---|---|---|---|
| Subject | NEC VR4300 |
E502251
|
entity |
| Predicate | instructionSetArchitecture |
P8609
|
FINISHED |
| Object | MIPS III |
—
|
NE NERFINISHED |
How this triple was built (2 steps)
Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.
NER
Named-entity recognition
gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: MIPS III | Statement: [NEC VR4300, instructionSetArchitecture, MIPS III]
NED1
Entity disambiguation (via context triple)
gpt-5-mini-2025-08-07
Target entity: MIPS III Context triple: [NEC VR4300, instructionSetArchitecture, MIPS III]
-
A.
MIPS III
chosen
MIPS III is a 64-bit RISC instruction set architecture in the MIPS family, extending earlier versions with larger address space and enhanced computational capabilities.
-
B.
MIPS IV
MIPS IV is a 64-bit RISC instruction set architecture in the MIPS family, designed to enhance performance and support advanced computing features over its predecessors.
-
C.
MIPS II
MIPS II is the second-generation version of the MIPS instruction set architecture, extending the original design with additional instructions and features for improved performance and functionality.
-
D.
MIPS V
MIPS V is a later revision of the MIPS instruction set architecture that extends earlier versions with enhanced support for 64-bit operations and improved performance features.
-
E.
MIPS R3000
The MIPS R3000 is a 32-bit RISC microprocessor widely used in late-1980s and early-1990s workstations, servers, and embedded systems.
- F. None of above.
- G. Unsure - the case is ambiguous/there is not enough information to decide.
Provenance (2 batches)
The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.
| Step | Stage | Batch ID | Status | When |
|---|---|---|---|---|
| creating | Elicitation | batch_69e0b4ae5f1081908768b0c9a3a0bf38 |
completed | April 16, 2026, 10:06 a.m. |
| NER | Named-entity recognition | batch_69e69962d810819091bb13fe73250e24 |
completed | April 20, 2026, 9:23 p.m. |
Created at: April 16, 2026, 11:33 a.m.