Triple
T20473368
| Position | Surface form | Disambiguated ID | Type / Status |
|---|---|---|---|
| Subject | Project Reality |
E502250
|
entity |
| Predicate | architectureBitWidth |
P107153
|
FINISHED |
| Object | 64-bit |
—
|
LITERAL FINISHED |
How this triple was built (2 steps)
Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.
NER
Named-entity recognition
gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: 64-bit | Statement: [Project Reality, architectureBitWidth, 64-bit]
PD
Predicate disambiguation
gpt-5-mini-2025-08-07
Target predicate: architectureBitWidth Context triple: [Project Reality, architectureBitWidth, 64-bit]
-
A.
bitWidth
Indicates the number of bits used to represent or encode a given value, type, or data element.
-
B.
cpuBits
chosen
Indicates the number of bits used by a CPU’s architecture or word size in the described context.
-
C.
busWidthComparedToISA
Indicates how the width of a bus compares to the width defined by a given instruction set architecture (ISA), such as being wider, narrower, or equal.
-
D.
numberOfGeneralPurposeRegisters
Indicates the quantity of general-purpose registers associated with or available in a given computing context.
-
E.
cpuArchitecture
Indicates the type of processor instruction set or hardware architecture that a computing system or component is designed to run on.
- F. None of above.
Provenance (3 batches)
The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.
| Step | Stage | Batch ID | Status | When |
|---|---|---|---|---|
| creating | Elicitation | batch_69e0b4ae5f1081908768b0c9a3a0bf38 |
completed | April 16, 2026, 10:06 a.m. |
| NER | Named-entity recognition | batch_69e69962d810819091bb13fe73250e24 |
completed | April 20, 2026, 9:23 p.m. |
| PD | Predicate disambiguation | batch_69e57679eb40819086142df3e39c928e |
completed | April 20, 2026, 12:42 a.m. |
Created at: April 16, 2026, 11:33 a.m.