Triple
T1718006
| Position | Surface form | Disambiguated ID | Type / Status |
|---|---|---|---|
| Subject | MIPS |
E37330
|
entity |
| Predicate | hasCallingConvention |
P31909
|
FINISHED |
| Object | n32 ABI |
E37330
|
NE FINISHED |
How this triple was built (2 steps)
Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.
NER
Named-entity recognition
gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: n32 ABI | Statement: [MIPS, hasCallingConvention, n32 ABI]
NED1
Entity disambiguation (via context triple)
gpt-5-mini-2025-08-07
Target entity: n32 ABI Context triple: [MIPS, hasCallingConvention, n32 ABI]
-
A.
IA-32
IA-32 is Intel’s 32-bit x86 architecture used as the basis for many generations of desktop, mobile, and embedded processors.
-
B.
ARM
ARM is a family of energy-efficient RISC processor architectures widely used in mobile devices, embedded systems, and increasingly in laptops and servers.
-
C.
GNU Binutils
GNU Binutils is a collection of binary tools, including assemblers, linkers, and related utilities, widely used in software development for compiling and manipulating executable programs and object files.
-
D.
MIPS
chosen
MIPS is a RISC (Reduced Instruction Set Computer) processor architecture widely used in embedded systems, networking equipment, and academic settings.
-
E.
RISC-V
RISC-V is an open, extensible instruction set architecture (ISA) based on the reduced instruction set computing (RISC) principles, widely used for research, embedded systems, and increasingly general-purpose computing.
- F. None of above.
- G. Unsure - the case is ambiguous/there is not enough information to decide.
Provenance (3 batches)
The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.
| Step | Stage | Batch ID | Status | When |
|---|---|---|---|---|
| creating | Elicitation | batch_69a8861912dc8190931af43b4b9158a7 |
completed | March 4, 2026, 7:20 p.m. |
| NER | Named-entity recognition | batch_69abaffc4e5c81908ce0b9cfe833445e |
completed | March 7, 2026, 4:56 a.m. |
| NED1 | Entity disambiguation (via context triple) | batch_69ad8ae6940c81909c1ebdfb0cdef5fc |
completed | March 8, 2026, 2:42 p.m. |
Created at: March 4, 2026, 7:30 p.m.