Triple
T1718004
| Position | Surface form | Disambiguated ID | Type / Status |
|---|---|---|---|
| Subject | MIPS |
E37330
|
entity |
| Predicate | commonlyTaughtWith |
P31908
|
FINISHED |
| Object | QtSPIM simulator |
E86734
|
NE FINISHED |
How this triple was built (2 steps)
Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.
NER
Named-entity recognition
gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: QtSPIM simulator | Statement: [MIPS, commonlyTaughtWith, QtSPIM simulator]
NED1
Entity disambiguation (via context triple)
gpt-5-mini-2025-08-07
Target entity: QtSPIM simulator Context triple: [MIPS, commonlyTaughtWith, QtSPIM simulator]
-
A.
SPIM
chosen
SPIM was the former ICAO airport code for Jorge Chávez International Airport in Lima, Peru, before it was changed to SPJC.
-
B.
Calliope mini
Calliope mini is a small educational microcontroller board designed to teach children and beginners programming and electronics through interactive projects.
-
C.
Keil
Keil is a German-origin surname borne by various notable individuals, including Portuguese composer Alfredo Keil.
-
D.
MIPS
MIPS is a RISC (Reduced Instruction Set Computer) processor architecture widely used in embedded systems, networking equipment, and academic settings.
-
E.
IEEE 1149.1 JTAG boundary‑scan standard
The IEEE 1149.1 JTAG boundary-scan standard is a widely used test and debug specification that defines a serial interface and architecture for accessing and testing the internal logic and interconnects of integrated circuits and circuit boards.
- F. None of above.
- G. Unsure - the case is ambiguous/there is not enough information to decide.
Provenance (3 batches)
The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.
| Step | Stage | Batch ID | Status | When |
|---|---|---|---|---|
| creating | Elicitation | batch_69a8861912dc8190931af43b4b9158a7 |
completed | March 4, 2026, 7:20 p.m. |
| NER | Named-entity recognition | batch_69abaffc4e5c81908ce0b9cfe833445e |
completed | March 7, 2026, 4:56 a.m. |
| NED1 | Entity disambiguation (via context triple) | batch_69ad8ae6940c81909c1ebdfb0cdef5fc |
completed | March 8, 2026, 2:42 p.m. |
Created at: March 4, 2026, 7:30 p.m.