Triple
T1717956
| Position | Surface form | Disambiguated ID | Type / Status |
|---|---|---|---|
| Subject | MIPS |
E37330
|
entity |
| Predicate | fullName |
P16
|
FINISHED |
| Object |
Microprocessor without Interlocked Pipeline Stages
Microprocessor without Interlocked Pipeline Stages (MIPS) is a RISC microprocessor architecture known for its simple, efficient design and widespread use in embedded systems, workstations, and educational settings.
|
E193757
|
NE FINISHED |
Provenance (5 batches)
| Stage | Batch ID | Job type | Status |
|---|---|---|---|
| creating | batch_69a8861912dc8190931af43b4b9158a7 |
elicitation | completed |
| NER | batch_69aa6337d8408190bdba8b50652d50ae |
ner | completed |
| NED1 | batch_69ad8ae6940c81909c1ebdfb0cdef5fc |
ned_source_triple | completed |
| NED2 | batch_69ad97b18f9c8190a9c5ed80b5ed0195 |
ned_description | completed |
| NEDg | batch_69ad957bd63c819099a508ca5c4102cc |
nedg | completed |
Created at: March 4, 2026, 7:30 p.m.