Triple
T16921898
| Position | Surface form | Disambiguated ID | Type / Status |
|---|---|---|---|
| Subject | RAD6000 |
E410461
|
entity |
| Predicate | instructionSetArchitecture |
P8609
|
FINISHED |
| Object | POWER ISA |
E216082
|
NE FINISHED |
How this triple was built (2 steps)
Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.
NER
Named-entity recognition
gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: POWER ISA | Statement: [RAD6000, instructionSetArchitecture, POWER ISA]
NED1
Entity disambiguation (via context triple)
gpt-5-mini-2025-08-07
Target entity: POWER ISA Context triple: [RAD6000, instructionSetArchitecture, POWER ISA]
-
A.
RISC-V
RISC-V is an open, extensible instruction set architecture (ISA) based on the reduced instruction set computing (RISC) principles, widely used for research, embedded systems, and increasingly general-purpose computing.
-
B.
Power ISA
Power ISA is IBM's modern 64-bit RISC instruction set architecture used in high-performance servers, embedded systems, and supercomputers, evolving from the earlier PowerPC architecture.
-
C.
POWER instruction set architecture
chosen
The POWER instruction set architecture is a reduced instruction set computing (RISC) architecture originally developed by IBM for high-performance servers and workstations, forming the basis for later PowerPC and Power Architecture designs.
-
D.
MIPS
MIPS is an infrared imaging and photometry instrument that operated aboard the Spitzer Space Telescope, used to study celestial objects at multiple mid- to far-infrared wavelengths.
-
E.
MIPS
MIPS is a RISC (Reduced Instruction Set Computer) processor architecture widely used in embedded systems, networking equipment, and academic settings.
- F. None of above.
- G. Unsure - the case is ambiguous/there is not enough information to decide.
Provenance (3 batches)
The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.
| Step | Stage | Batch ID | Status | When |
|---|---|---|---|---|
| creating | Elicitation | batch_69d886c7b1e481908c3766dfa8c13458 |
completed | April 10, 2026, 5:12 a.m. |
| NER | Named-entity recognition | batch_69e3cdef7df881908b69aa3c4f50ef94 |
completed | April 18, 2026, 6:31 p.m. |
| NED1 | Entity disambiguation (via context triple) | batch_6a00cfd3c488819089e3791c7e704baf |
completed | May 10, 2026, 6:34 p.m. |
Created at: April 10, 2026, 5:30 a.m.