Triple

Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).

Phrase: IEEE 1800-2009 | Statement: [SystemVerilog, hasRevision, IEEE 1800-2009]

Target entity: IEEE 1800-2009
Context triple: [SystemVerilog, hasRevision, IEEE 1800-2009]

• A. IEEE 1364
  IEEE 1364 is the IEEE standard that defines the Verilog hardware description language used for modeling and designing digital electronic systems.
• B. SystemVerilog
  SystemVerilog is a hardware description and verification language widely used to design, model, and verify complex digital integrated circuits and systems.
• C. Bluespec SystemVerilog
  Bluespec SystemVerilog is a high-level hardware description language that extends Verilog with rule-based, functional programming concepts to enable more abstract and formally verifiable hardware design.
• D. Verilog
  Verilog is a hardware description language (HDL) used to model, design, and verify digital circuits and systems such as those implemented in CPLDs and FPGAs.
• E. IEEE 1149.10
  IEEE 1149.10 is a JTAG-related IEEE standard that defines high-speed test access mechanisms for embedded instrumentation and system-level testing of complex digital devices and boards.
• F. None of above. chosen
• G. Unsure - the case is ambiguous/there is not enough information to decide.

Generate a one-sentence description of the target entity. 
You are given a context triple in the form (subject, predicate, object), where the object is the target entity. 
# Instructions
Use the triple to infer relevant information about the entity. Describe the entity based on what is most defining, well-known. 
Avoid repeating the information from the triple, unless really essential.
# Response Format
Return only the sentence: "Description: [one-sentence description of the target entity]"

Entity: IEEE 1800-2009
Triple: [SystemVerilog, hasRevision, IEEE 1800-2009]

IEEE 1800-2009 is a standardized revision of the SystemVerilog hardware description and verification language that consolidates and updates its features for digital design and verification.

Target entity: IEEE 1800-2009
Target entity description: IEEE 1800-2009 is a standardized revision of the SystemVerilog hardware description and verification language that consolidates and updates its features for digital design and verification.

• A. IEEE 1364
  IEEE 1364 is the IEEE standard that defines the Verilog hardware description language used for modeling and designing digital electronic systems.
• B. SystemVerilog chosen
  SystemVerilog is a hardware description and verification language widely used to design, model, and verify complex digital integrated circuits and systems.
• C. Bluespec SystemVerilog
  Bluespec SystemVerilog is a high-level hardware description language that extends Verilog with rule-based, functional programming concepts to enable more abstract and formally verifiable hardware design.
• D. Verilog
  Verilog is a hardware description language (HDL) used to model, design, and verify digital circuits and systems such as those implemented in CPLDs and FPGAs.
• E. IEEE 1149.10
  IEEE 1149.10 is a JTAG-related IEEE standard that defines high-speed test access mechanisms for embedded instrumentation and system-level testing of complex digital devices and boards.
• F. None of above.