Triple
T15304802
| Position | Surface form | Disambiguated ID | Type / Status |
|---|---|---|---|
| Subject | SystemVerilog |
E365872
|
entity |
| Predicate | hasRevision |
P5571
|
FINISHED |
| Object | IEEE 1800-2005 |
E365872
|
NE FINISHED |
How this triple was built (2 steps)
Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.
NER
Named-entity recognition
gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: IEEE 1800-2005 | Statement: [SystemVerilog, hasRevision, IEEE 1800-2005]
NED1
Entity disambiguation (via context triple)
gpt-5-mini-2025-08-07
Target entity: IEEE 1800-2005 Context triple: [SystemVerilog, hasRevision, IEEE 1800-2005]
-
A.
IEEE 1364
IEEE 1364 is the IEEE standard that defines the Verilog hardware description language used for modeling and designing digital electronic systems.
-
B.
Bluespec SystemVerilog
Bluespec SystemVerilog is a high-level hardware description language that extends Verilog with rule-based, functional programming concepts to enable more abstract and formally verifiable hardware design.
-
C.
SystemVerilog
chosen
SystemVerilog is a hardware description and verification language widely used to design, model, and verify complex digital integrated circuits and systems.
-
D.
Verilog
Verilog is a hardware description language (HDL) used to model, design, and verify digital circuits and systems such as those implemented in CPLDs and FPGAs.
-
E.
Altera Hardware Description Language
Altera Hardware Description Language (AHDL) is a proprietary hardware description language developed by Altera for designing and implementing digital logic circuits on its programmable logic devices.
- F. None of above.
- G. Unsure - the case is ambiguous/there is not enough information to decide.
Provenance (3 batches)
The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.
| Step | Stage | Batch ID | Status | When |
|---|---|---|---|---|
| creating | Elicitation | batch_69d85a113ee881908e297a1d38dd79fa |
completed | April 10, 2026, 2:01 a.m. |
| NER | Named-entity recognition | batch_69e03ccef14c819099c5ebe962e7f867 |
completed | April 16, 2026, 1:35 a.m. |
| NED1 | Entity disambiguation (via context triple) | batch_69ff01e47d8c8190844d45dda9a3e5ea |
completed | May 9, 2026, 9:44 a.m. |
Created at: April 10, 2026, 3:16 a.m.