Triple
T14086594
| Position | Surface form | Disambiguated ID | Type / Status |
|---|---|---|---|
| Subject | RISC I |
E339011
|
entity |
| Predicate | category |
P87
|
FINISHED |
| Object | Berkeley RISC project processors |
E193746
|
NE FINISHED |
How this triple was built (2 steps)
Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.
NER
Named-entity recognition
gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: Berkeley RISC project processors | Statement: [RISC I, category, Berkeley RISC project processors]
NED1
Entity disambiguation (via context triple)
gpt-5-mini-2025-08-07
Target entity: Berkeley RISC project processors Context triple: [RISC I, category, Berkeley RISC project processors]
-
A.
Berkeley RISC projects
chosen
The Berkeley RISC projects were pioneering academic research efforts at the University of California, Berkeley that developed early Reduced Instruction Set Computer architectures, profoundly influencing modern processor design.
-
B.
SPARC microprocessor architecture
The SPARC microprocessor architecture is a RISC-based instruction set architecture widely used in high-performance and enterprise servers, originally created to power scalable, multi-processor systems.
-
C.
RISC architecture
RISC architecture is a CPU design philosophy that uses a small, highly optimized set of simple instructions to achieve high performance and efficiency.
-
D.
Acorn RISC Machine
Acorn RISC Machine (ARM) is a family of energy-efficient reduced instruction set computer (RISC) architectures widely used in mobile devices, embedded systems, and increasingly in servers and personal computers.
-
E.
Precision Architecture – Reduced Instruction Set Computing
Precision Architecture – Reduced Instruction Set Computing (PA-RISC) is Hewlett-Packard’s proprietary RISC microprocessor architecture designed to deliver high performance and efficiency in HP workstations and servers.
- F. None of above.
- G. Unsure - the case is ambiguous/there is not enough information to decide.
Provenance (3 batches)
The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.
| Step | Stage | Batch ID | Status | When |
|---|---|---|---|---|
| creating | Elicitation | batch_69d81c687b0c819087fd9ed4198403f8 |
completed | April 9, 2026, 9:38 p.m. |
| NER | Named-entity recognition | batch_69de5edff1b881909ea56dc2429ef2dd |
completed | April 14, 2026, 3:36 p.m. |
| NED1 | Entity disambiguation (via context triple) | batch_69fcdefe88b481908b3dca1f019e7809 |
completed | May 7, 2026, 6:50 p.m. |
Created at: April 9, 2026, 10:21 p.m.