Triple
T14086561
| Position | Surface form | Disambiguated ID | Type / Status |
|---|---|---|---|
| Subject | RISC I |
E339011
|
entity |
| Predicate | influenced |
P9
|
FINISHED |
| Object | RISC II |
E339012
|
NE FINISHED |
How this triple was built (2 steps)
Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.
NER
Named-entity recognition
gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: RISC II | Statement: [RISC I, influenced, RISC II]
NED1
Entity disambiguation (via context triple)
gpt-5-mini-2025-08-07
Target entity: RISC II Context triple: [RISC I, influenced, RISC II]
-
A.
RISC II
chosen
RISC II is an early experimental reduced instruction set computer (RISC) processor developed at UC Berkeley that significantly shaped the design of later RISC architectures.
-
B.
Risc PC
Risc PC is a modular personal computer introduced by Acorn Computers in the 1990s, known for its RISC-based architecture and expandability.
-
C.
POWER2 RISC processor
The POWER2 RISC processor is IBM’s second-generation high-performance Reduced Instruction Set Computing microprocessor, used primarily in RS/6000 workstations and servers during the early to mid-1990s.
-
D.
MIPS R2000
The MIPS R2000 is an early 32-bit RISC microprocessor that helped popularize the MIPS architecture in academic and commercial systems during the late 1980s.
-
E.
MIPS II
MIPS II is the second-generation version of the MIPS instruction set architecture, extending the original design with additional instructions and features for improved performance and functionality.
- F. None of above.
- G. Unsure - the case is ambiguous/there is not enough information to decide.
Provenance (3 batches)
The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.
| Step | Stage | Batch ID | Status | When |
|---|---|---|---|---|
| creating | Elicitation | batch_69d81c687b0c819087fd9ed4198403f8 |
completed | April 9, 2026, 9:38 p.m. |
| NER | Named-entity recognition | batch_69de5edff1b881909ea56dc2429ef2dd |
completed | April 14, 2026, 3:36 p.m. |
| NED1 | Entity disambiguation (via context triple) | batch_69fcd0a3e55c81909b52f618e9076dd2 |
completed | May 7, 2026, 5:49 p.m. |
Created at: April 9, 2026, 10:21 p.m.