Triple

T13410493
Position Surface form Disambiguated ID Type / Status
Subject Fugaku E320072 entity
Predicate processorExtension P74581 FINISHED
Object Scalable Vector Extension E732964 NE FINISHED

How this triple was built (3 steps)

Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.

NER Named-entity recognition gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: Scalable Vector Extension | Statement: [Fugaku, processorExtension, Scalable Vector Extension]
NED1 Entity disambiguation (via context triple) gpt-5-mini-2025-08-07
Target entity: Scalable Vector Extension
Context triple: [Fugaku, processorExtension, Scalable Vector Extension]
  • A. V (vector extension)
    V (vector extension) is the RISC-V standard for scalable vector processing, enabling efficient parallel computation on variable-length data vectors.
  • B. ARM SVE chosen
    ARM SVE (Scalable Vector Extension) is an ARM architecture extension that provides flexible, length-agnostic vector processing capabilities aimed at high-performance computing and data-intensive workloads.
  • C. AVX-512
    AVX-512 is an advanced SIMD instruction set for x86 processors that enables high-throughput parallel processing using 512-bit wide vector operations.
  • D. P (packed-SIMD extension)
    P (packed-SIMD extension) is a RISC-V instruction set extension that adds packed single-instruction multiple-data operations to accelerate parallel data processing tasks such as signal processing and multimedia workloads.
  • E. Intel AVX2
    Intel AVX2 is an x86 instruction set extension from Intel that enhances performance for integer-heavy and vectorized workloads through wider SIMD operations and new vector instructions.
  • F. None of above.
  • G. Unsure - the case is ambiguous/there is not enough information to decide.
PD Predicate disambiguation gpt-5-mini-2025-08-07
Target predicate: processorExtension
Context triple: [Fugaku, processorExtension, Scalable Vector Extension]
  • A. formerExtension
    Indicates that one entity previously served as an extension or subsidiary part of another entity, but no longer holds that status.
  • B. instructionSetExtension
    Indicates that one instruction set architecture extends or augments another with additional instructions or capabilities.
  • C. definesExtension
    Indicates that one entity specifies or establishes the extension, scope, or detailed form of another entity.
  • D. instructionSetExtensions chosen
    Indicates that one entity defines, supports, or includes additional instruction set features or extensions relative to another.
  • E. backendExtension
    Indicates that one entity functions as an extension or add-on to another entity’s backend system or service.
  • F. None of above.

Provenance (4 batches)

The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.

Step Stage Batch ID Status When
creating Elicitation batch_69d806b943cc8190b6af624d385d7e12 completed April 9, 2026, 8:06 p.m.
NER Named-entity recognition batch_69dbaeb3facc819088c1af3b59237e7a completed April 12, 2026, 2:39 p.m.
NED1 Entity disambiguation (via context triple) batch_69f7307ccff08190aa4037aa5a48f7d0 completed May 3, 2026, 11:24 a.m.
PD Predicate disambiguation batch_69d9a0355de48190bb3fb96912e20df3 completed April 11, 2026, 1:13 a.m.
Created at: April 9, 2026, 9:35 p.m.