Triple

T11214093
Position Surface form Disambiguated ID Type / Status
Subject John L. Hennessy E265385 entity
Predicate coFounded P104 FINISHED
Object MIPS Computer Systems
MIPS Computer Systems was a pioneering computer hardware company best known for developing the influential MIPS RISC microprocessor architecture.
E37330 NE FINISHED

How this triple was built (4 steps)

Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.

NER Named-entity recognition gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: MIPS Computer Systems | Statement: [John L. Hennessy, coFounded, MIPS Computer Systems]
NED1 Entity disambiguation (via context triple) gpt-5-mini-2025-08-07
Target entity: MIPS Computer Systems
Context triple: [John L. Hennessy, coFounded, MIPS Computer Systems]
  • A. MIPS R2000
    The MIPS R2000 is an early 32-bit RISC microprocessor that helped popularize the MIPS architecture in academic and commercial systems during the late 1980s.
  • B. MIPS R5000
    The MIPS R5000 is a 64-bit RISC microprocessor from the MIPS family, widely used in mid-1990s workstations and embedded systems for its balance of performance and cost.
  • C. MIPS R4600
    The MIPS R4600 is a 64-bit RISC microprocessor from the MIPS family, widely used in mid-1990s workstations and embedded systems for its balance of performance and cost.
  • D. MIPS II
    MIPS II is the second-generation version of the MIPS instruction set architecture, extending the original design with additional instructions and features for improved performance and functionality.
  • E. MIPS
    MIPS is a RISC (Reduced Instruction Set Computer) processor architecture widely used in embedded systems, networking equipment, and academic settings.
  • F. None of above. chosen
  • G. Unsure - the case is ambiguous/there is not enough information to decide.
NEDg Description generation gpt-5.1
Instruction
Generate a one-sentence description of the target entity. 
You are given a context triple in the form (subject, predicate, object), where the object is the target entity. 
# Instructions
Use the triple to infer relevant information about the entity. Describe the entity based on what is most defining, well-known. 
Avoid repeating the information from the triple, unless really essential.
# Response Format
Return only the sentence: "Description: [one-sentence description of the target entity]"
Input
Entity: MIPS Computer Systems
Triple: [John L. Hennessy, coFounded, MIPS Computer Systems]
Generated description
MIPS Computer Systems was a pioneering computer hardware company best known for developing the influential MIPS RISC microprocessor architecture.
NED2 Entity disambiguation (via description) gpt-5-mini-2025-08-07
Target entity: MIPS Computer Systems
Target entity description: MIPS Computer Systems was a pioneering computer hardware company best known for developing the influential MIPS RISC microprocessor architecture.
  • A. MIPS R2000
    The MIPS R2000 is an early 32-bit RISC microprocessor that helped popularize the MIPS architecture in academic and commercial systems during the late 1980s.
  • B. MIPS R5000
    The MIPS R5000 is a 64-bit RISC microprocessor from the MIPS family, widely used in mid-1990s workstations and embedded systems for its balance of performance and cost.
  • C. MIPS R4600
    The MIPS R4600 is a 64-bit RISC microprocessor from the MIPS family, widely used in mid-1990s workstations and embedded systems for its balance of performance and cost.
  • D. MIPS II
    MIPS II is the second-generation version of the MIPS instruction set architecture, extending the original design with additional instructions and features for improved performance and functionality.
  • E. MIPS chosen
    MIPS is a RISC (Reduced Instruction Set Computer) processor architecture widely used in embedded systems, networking equipment, and academic settings.
  • F. None of above.

Provenance (5 batches)

The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.

Step Stage Batch ID Status When
creating Elicitation batch_69d6aac59460819089b9848b27f57848 completed April 8, 2026, 7:21 p.m.
NER Named-entity recognition batch_69d7e8d7f47c8190b78c640ff1a01943 completed April 9, 2026, 5:58 p.m.
NED1 Entity disambiguation (via context triple) batch_69e497569efc8190b8e9cb6b1db3f94d completed April 19, 2026, 8:50 a.m.
NEDg Description generation batch_69e49c0a92b08190ac5debb7d67ca776 completed April 19, 2026, 9:10 a.m.
NED2 Entity disambiguation (via description) batch_69e49e8dc4ec81908d0defe77827d197 completed April 19, 2026, 9:21 a.m.
Created at: April 8, 2026, 9:30 p.m.