instructionCacheSize
P86697
predicate
Indicates the size or capacity of the instruction cache associated with a processor or computing component.
Observed surface forms (5)
- cacheSize ×6
- primaryCacheSize ×4
- l1InstructionCachePerCore ×2
- L1InstructionCachePerCore ×1
- onChipCacheSizeInstruction ×1
Sample triples (16)
| Subject | Object |
|---|---|
| A13 Bionic | 128 KB via predicate surface "l1InstructionCachePerCore" ⓘ |
| Hitachi SH-2 | 4 KB via predicate surface "cacheSize" ⓘ |
| Intel Core i5-7Y54 | 4 MB via predicate surface "cacheSize" ⓘ |
| MIPS R4600 | 16 KB data cache via predicate surface "primaryCacheSize" ⓘ |
| MIPS R4600 | 16 KB instruction cache via predicate surface "primaryCacheSize" ⓘ |
|
Motorola 68020 microprocessor
surface form:
Motorola 68020
|
256 bytes ⓘ |
|
Motorola 68030 microprocessor
surface form:
Motorola 68030
|
256 bytes ⓘ |
|
Motorola 68040 microprocessor
surface form:
Motorola 68040
|
4 KB data cache via predicate surface "cacheSize" ⓘ |
|
Motorola 68040 microprocessor
surface form:
Motorola 68040
|
4 KB instruction cache via predicate surface "cacheSize" ⓘ |
| Motorola 68060 | 8 KB via predicate surface "onChipCacheSizeInstruction" ⓘ |
|
64-bit NEC VR4300
surface form:
NEC VR4300
|
16 KB instruction cache via predicate surface "primaryCacheSize" ⓘ |
|
64-bit NEC VR4300
surface form:
NEC VR4300
|
8 KB data cache via predicate surface "primaryCacheSize" ⓘ |
| R4000 | 8 KB data cache via predicate surface "cacheSize" ⓘ |
| R4000 | 8 KB instruction cache via predicate surface "cacheSize" ⓘ |
| UltraSPARC T1 | 16 KB via predicate surface "L1InstructionCachePerCore" ⓘ |
| UltraSPARC T2 | 16 KB via predicate surface "l1InstructionCachePerCore" ⓘ |