instructionCacheSize

P86697
predicate

Indicates the size or capacity of the instruction cache associated with a processor or computing component.

Try in SPARQL

All labels observed (6)

Label Occurrences
cacheSize 6
primaryCacheSize 4
instructionCacheSize canonical 2

Description generation (PDg)

The one-sentence description above was generated by prompting gpt-5.1 with the predicate name and this instruction.

Instruction
Given a predicate that represents a relationship or action between entities, generate a one-sentence description explaining its meaning.  
# Instructions
Focus on describing the relationship, not the entities themselves. 
# Response Format
Begin the description with \' Indicates...\'
Input
Predicate: instructionCacheSize
Generated description
Indicates the size or capacity of the instruction cache associated with a processor or computing component.

Sample triples (16)

Subject Object
Motorola 68020 microprocessor
surface form: Motorola 68020
256 bytes ⓘ
Motorola 68030 microprocessor
surface form: Motorola 68030
256 bytes ⓘ
Motorola 68040 microprocessor
surface form: Motorola 68040
4 KB instruction cache via predicate surface "cacheSize" ⓘ
Motorola 68040 microprocessor
surface form: Motorola 68040
4 KB data cache via predicate surface "cacheSize" ⓘ
Motorola 68060 8 KB via predicate surface "onChipCacheSizeInstruction" ⓘ
UltraSPARC T1 16 KB via predicate surface "L1InstructionCachePerCore" ⓘ
UltraSPARC T2 16 KB via predicate surface "l1InstructionCachePerCore" ⓘ
64-bit NEC VR4300
surface form: NEC VR4300
16 KB instruction cache via predicate surface "primaryCacheSize" ⓘ
64-bit NEC VR4300
surface form: NEC VR4300
8 KB data cache via predicate surface "primaryCacheSize" ⓘ
MIPS R4600 16 KB instruction cache via predicate surface "primaryCacheSize" ⓘ
MIPS R4600 16 KB data cache via predicate surface "primaryCacheSize" ⓘ
Intel Core i5-7Y54 4 MB via predicate surface "cacheSize" ⓘ
R4000 8 KB instruction cache via predicate surface "cacheSize" ⓘ
R4000 8 KB data cache via predicate surface "cacheSize" ⓘ
Hitachi SH-2 4 KB via predicate surface "cacheSize" ⓘ
A13 Bionic 128 KB via predicate surface "l1InstructionCachePerCore" ⓘ