TSMC N7P
E938596
TSMC N7P is an enhanced 7-nanometer semiconductor manufacturing process from TSMC that offers improved performance and power efficiency over its predecessor and is used for advanced mobile and computing chips.
Statements (46)
| Predicate | Object |
|---|---|
| instanceOf |
TSMC 7 nm process variant
ⓘ
semiconductor manufacturing process ⓘ |
| commercialAvailability | mass production by late 2010s ⓘ |
| competesWith | Samsung 7 nm LPP process ⓘ |
| countryOfManufacture | Taiwan NERFINISHED ⓘ |
| density | similar to TSMC N7 ⓘ |
| designEntry | uses same PDK generation as N7 with enhancements ⓘ |
| designGoal | drop‑in upgrade path from N7 ⓘ |
| designReuse | allows reuse of N7 IP with minimal changes ⓘ |
| designRuleCompatibility | fully compatible with TSMC N7 design rules ⓘ |
| ecosystem | supported by major EDA vendors ⓘ |
| family | TSMC 7 nm family NERFINISHED ⓘ |
| improvementOver | TSMC N7 NERFINISHED ⓘ |
| introducedBy | Taiwan Semiconductor Manufacturing Company Limited NERFINISHED ⓘ |
| libraryCompatibility | compatible with many N7 standard cell libraries ⓘ |
| lithographyType | DUV ⓘ |
| manufacturer | TSMC NERFINISHED ⓘ |
| marketingPosition | performance‑enhanced 7 nm process ⓘ |
| marketSegment |
data‑center and server processors
ⓘ
high‑end consumer electronics ⓘ premium smartphones ⓘ |
| maskCount | similar mask count to TSMC N7 ⓘ |
| nodeClass | advanced logic process ⓘ |
| optimizationFocus |
performance optimization
ⓘ
power optimization ⓘ |
| performance | improved vs TSMC N7 ⓘ |
| performanceGainOverPredecessor | up to 7% at same power ⓘ |
| powerEfficiency | improved vs TSMC N7 ⓘ |
| powerPerformanceAreaTradeoff | better power and performance at similar area to N7 ⓘ |
| powerReductionOverPredecessor | up to 10% at same performance ⓘ |
| predecessor | TSMC N7 NERFINISHED ⓘ |
| processNode | 7 nm ⓘ |
| requiresDesignMigration | no full redesign required from N7 ⓘ |
| successor |
TSMC N6
NERFINISHED
ⓘ
TSMC N7+ (N7 Plus) NERFINISHED ⓘ |
| supports |
advanced computing chips
ⓘ
advanced mobile chipsets ⓘ |
| targetApplications |
GPUs
ⓘ
application processors ⓘ high‑performance computing chips ⓘ mobile SoCs ⓘ networking ASICs ⓘ |
| transistorType | FinFET NERFINISHED ⓘ |
| usedIn | various flagship mobile SoCs of late 2010s ⓘ |
| usesEUV | no ⓘ |
| waferSize | 300 mm ⓘ |
Referenced by (1)
Full triples — surface form annotated when it differs from this entity's canonical label.