VLIW
E904642
VLIW (Very Long Instruction Word) is a computer processor architecture that executes multiple operations in parallel by encoding them into a single long instruction word, relying heavily on compiler optimization for performance.
Statements (49)
| Predicate | Object |
|---|---|
| instanceOf |
computer processor architecture
ⓘ
instruction set architecture paradigm ⓘ |
| abbreviationOf | Very Long Instruction Word NERFINISHED ⓘ |
| advantage |
lower power consumption potential
ⓘ
potentially high performance on regular workloads ⓘ reduced hardware complexity compared to superscalar ⓘ simpler control logic ⓘ |
| contrastsWith |
dynamic scheduling in hardware
ⓘ
out-of-order execution ⓘ superscalar architecture ⓘ |
| designGoal |
exploit parallelism at compile time
ⓘ
shift scheduling complexity to the compiler ⓘ simplify hardware complexity ⓘ |
| disadvantage |
binary compatibility issues across implementations
ⓘ
code size increase due to long instruction words ⓘ difficulty handling irregular control flow ⓘ heavy dependence on compiler quality ⓘ sensitivity to pipeline stalls ⓘ |
| enables | instruction-level parallelism ⓘ |
| encodes | multiple operations into a single long instruction word ⓘ |
| executes | multiple operations in parallel ⓘ |
| fullName | Very Long Instruction Word NERFINISHED ⓘ |
| hasCharacteristic |
exposes functional units directly to the compiler
ⓘ
fixed-width instruction bundles ⓘ limited hardware hazard detection ⓘ multiple operation fields per instruction word ⓘ simple instruction dispatch hardware ⓘ statically scheduled instruction issue ⓘ |
| historicalContext |
developed by Josh Fisher and colleagues at Yale and Multiflow
ⓘ
proposed in the 1980s ⓘ |
| influenced |
EPIC architecture
NERFINISHED
ⓘ
Itanium architecture NERFINISHED ⓘ |
| parallelismType | instruction-level parallelism ⓘ |
| relatedTo |
EPIC (Explicitly Parallel Instruction Computing)
NERFINISHED
ⓘ
Very Long Instruction Word DSPs NERFINISHED ⓘ |
| reliesOn |
compiler optimization
ⓘ
static scheduling by the compiler ⓘ |
| requires |
advanced compiler technology
ⓘ
aggressive instruction scheduling ⓘ software-based dependency analysis ⓘ software-based speculation and predication support ⓘ |
| schedulingType | static scheduling ⓘ |
| typicalFeature |
multiple functional units per core
ⓘ
predicated execution support ⓘ software pipelining support ⓘ |
| usedIn |
digital signal processors
ⓘ
embedded systems ⓘ media processing processors ⓘ some general-purpose CPUs ⓘ |
Referenced by (1)
Full triples — surface form annotated when it differs from this entity's canonical label.