Vivado Design Suite

E822028

electronic design automation software integrated development environment

Vivado Design Suite is Xilinx’s integrated development environment for designing, simulating, and implementing digital circuits on its FPGA and SoC devices.

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Statements (78)

Predicate	Object
instanceOf	electronic design automation software ⓘ integrated development environment ⓘ
developer	AMD NERFINISHED ⓘ Xilinx NERFINISHED ⓘ
feature	IP catalog ⓘ block design environment ⓘ constraint management ⓘ design rule checking ⓘ floorplanning ⓘ functional simulation ⓘ gate-level simulation ⓘ hardware debugging ⓘ incremental compilation ⓘ logic synthesis ⓘ on-chip logic analyzer ⓘ partial reconfiguration support ⓘ place and route ⓘ power analysis ⓘ timing analysis ⓘ
hasEdition	Vivado Design Edition NERFINISHED ⓘ Vivado HLx Editions NERFINISHED ⓘ Vivado System Edition NERFINISHED ⓘ Vivado WebPACK NERFINISHED ⓘ
includesComponent	Vivado HLS NERFINISHED ⓘ Vivado Hardware Manager NERFINISHED ⓘ Vivado IDE NERFINISHED ⓘ Vivado IP Integrator NERFINISHED ⓘ Vivado Implementation NERFINISHED ⓘ Vivado Simulator NERFINISHED ⓘ Vivado Synthesis NERFINISHED ⓘ Vivado Tcl Console NERFINISHED ⓘ
inputFormat	EDIF netlist ⓘ HDL source files ⓘ XDC constraints ⓘ
integratesWith	Vitis Unified Software Platform NERFINISHED ⓘ Xilinx SDK (legacy) NERFINISHED ⓘ
licenseModel	floating license ⓘ node-locked license ⓘ proprietary ⓘ
operatingSystem	Linux ⓘ Windows ⓘ
outputFormat	bitstream file ⓘ hardware handoff file ⓘ power reports ⓘ timing reports ⓘ
primaryUse	FPGA design ⓘ SoC design ⓘ digital circuit design ⓘ
publisher	AMD NERFINISHED ⓘ Xilinx NERFINISHED ⓘ
replaced	ISE Design Suite NERFINISHED ⓘ
supportsDebugFeature	Integrated Logic Analyzer GENERATED ⓘ JTAG-based debugging GENERATED ⓘ Virtual I/O GENERATED ⓘ
supportsFlow	IP-centric design ⓘ RTL-to-bitstream ⓘ block-based design ⓘ high-level synthesis flow ⓘ
supportsLanguage	C ⓘ C++ ⓘ SystemVerilog NERFINISHED ⓘ Tcl NERFINISHED ⓘ VHDL NERFINISHED ⓘ Verilog NERFINISHED ⓘ
supportsPlatform	FPGA ⓘ SoC NERFINISHED ⓘ
supportsVendorDevice	Artix-7 GENERATED ⓘ Kintex UltraScale GENERATED ⓘ Kintex-7 GENERATED ⓘ Virtex UltraScale GENERATED ⓘ Virtex-7 GENERATED ⓘ Xilinx FPGA GENERATED ⓘ Xilinx SoC GENERATED ⓘ Zynq UltraScale+ GENERATED ⓘ Zynq-7000 GENERATED ⓘ
targetUser	FPGA designers ⓘ digital hardware engineers ⓘ embedded system designers ⓘ

Referenced by (1)

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Xilinx → product → Vivado Design Suite ⓘ