MIPS R2000

E819631

The MIPS R2000 is an early 32-bit RISC microprocessor that helped popularize the MIPS architecture in academic and commercial systems during the late 1980s.

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Statements (46)

Predicate Object
instanceOf microprocessor
addressSpace 32-bit
architecture MIPS I NERFINISHED
branchDelaySlots 1
cacheSupport external instruction and data caches
clockFrequencyRange 8 MHz to 16 MHz
commercialAvailabilityYear 1986
coprocessorInterfaceCount 4
designStyle load-store architecture
family MIPS R-series NERFINISHED
floatingPointCoprocessor MIPS R2010 NERFINISHED
influenced RISC processor education
later MIPS processor designs
instructionSetType reduced instruction set computing
integerRegisterWidth 32-bit
introducedBy MIPS Computer Systems NERFINISHED
introducedInYear 1985
marketPosition early commercial RISC CPU
MMUImplementation in coprocessor 0
notability helped popularize the MIPS architecture in academia and industry
notableSystemUsage DECstation workstations GENERATED
MIPS Magnum workstations GENERATED
onChipCache no
pipelineStages 5
pipelineType scalar pipeline
registerFileSize 32 general-purpose registers
successor MIPS R3000 NERFINISHED
supportsBigEndian yes GENERATED
supportsCoprocessor CP0 GENERATED
CP1 GENERATED
CP2 GENERATED
CP3 GENERATED
supportsFloatingPointVia MIPS R2010 GENERATED
supportsHardwareDivide yes GENERATED
supportsHardwareMultiply yes GENERATED
supportsLittleEndian no GENERATED
supportsMultiplyDivideUnit yes GENERATED
supportsVirtualAddressTranslation yes GENERATED
technologyNode 1.5 µm CMOS (typical implementations)
transistorCountApproximate 115000
usedIn embedded systems
servers
workstations
usesDelayedBranches yes
virtualMemorySupport yes
wordSize 32-bit

Referenced by (1)

Full triples — surface form annotated when it differs from this entity's canonical label.

MC88100 competition MIPS R2000