POWER Architecture, first generation
E758591
POWER Architecture, first generation refers to IBM’s original POWER1 RISC microprocessor design that formed the basis for the later POWER and PowerPC processor families.
Statements (47)
| Predicate | Object |
|---|---|
| instanceOf |
IBM POWER architecture generation
ⓘ
RISC architecture ⓘ microprocessor architecture ⓘ |
| alsoKnownAs | POWER1 architecture NERFINISHED ⓘ |
| ancestorOf |
POWER3 architecture
NERFINISHED
ⓘ
POWER4 architecture NERFINISHED ⓘ modern IBM POWER processors ⓘ |
| basedOn |
IBM 801 project
NERFINISHED
ⓘ
IBM America Project ⓘ |
| commercializationEra | early 1990s ⓘ |
| designedFor | high-performance UNIX systems ⓘ |
| designGoal |
high floating-point performance
ⓘ
scalability for servers and workstations ⓘ |
| developer | IBM ⓘ |
| endianSupport | big-endian ⓘ |
| hasFeature |
branch processing unit
ⓘ
fixed-length instructions ⓘ load-store architecture ⓘ pipelined execution units ⓘ register-to-register operations ⓘ separate integer and floating-point units ⓘ |
| hasRegisterType |
condition register
ⓘ
count register ⓘ floating-point registers ⓘ general-purpose registers ⓘ link register ⓘ |
| influenced |
PowerPC instruction set architecture
NERFINISHED
ⓘ
later POWER2 design ⓘ |
| instructionSetType | reduced instruction set computing ⓘ |
| introducedBy | IBM RS/6000 workstations NERFINISHED ⓘ |
| introducedInProductLine | IBM RS/6000 servers NERFINISHED ⓘ |
| marketedFor |
enterprise servers
ⓘ
technical workstations ⓘ |
| partOfFamily | IBM POWER architecture family NERFINISHED ⓘ |
| primaryVendor | IBM NERFINISHED ⓘ |
| runsOperatingSystem | AIX NERFINISHED ⓘ |
| successor |
POWER Architecture, second generation
NERFINISHED
ⓘ
PowerPC architecture NERFINISHED ⓘ |
| supports |
branch prediction
ⓘ
floating-point operations ⓘ integer operations ⓘ out-of-order execution (at implementation level in POWER1) ⓘ superscalar execution ⓘ |
| usedIn |
IBM POWER1 microprocessor
NERFINISHED
ⓘ
IBM POWER1+ microprocessor NERFINISHED ⓘ early IBM RS/6000 models ⓘ |
| wordSize | 32-bit ⓘ |
Referenced by (1)
Full triples — surface form annotated when it differs from this entity's canonical label.