MIPS IV
E727374
MIPS IV is a 64-bit RISC instruction set architecture in the MIPS family, designed to enhance performance and support advanced computing features over its predecessors.
All labels observed (1)
| Label | Occurrences |
|---|---|
| MIPS IV canonical | 1 |
How this entity was disambiguated
This entity first appeared as the object of triple T8284549 — resolving that mention is where its identity was fixed. The disambiguator weighed these candidate entities and picked the highlighted one (or “None”, minting a new entity). This is how homonymy is resolved: the same surface form can point to different entities.
NED1
Entity disambiguation (via context triple)
gpt-5-mini-2025-08-07
Target entity: MIPS IV Context triple: [Microprocessor without Interlocked Pipeline Stages, hasVariant, MIPS IV]
-
A.
MIPS III
MIPS III is a 64-bit RISC instruction set architecture in the MIPS family, extending earlier versions with larger address space and enhanced computational capabilities.
-
B.
MIPS II
MIPS II is the second-generation version of the MIPS instruction set architecture, extending the original design with additional instructions and features for improved performance and functionality.
-
C.
MIPS R4600
The MIPS R4600 is a 64-bit RISC microprocessor from the MIPS family, widely used in mid-1990s workstations and embedded systems for its balance of performance and cost.
-
D.
MIPS R5000
The MIPS R5000 is a 64-bit RISC microprocessor from the MIPS family, widely used in mid-1990s workstations and embedded systems for its balance of performance and cost.
-
E.
MIPS
MIPS is a RISC (Reduced Instruction Set Computer) processor architecture widely used in embedded systems, networking equipment, and academic settings.
- F. None of above. chosen
- G. Unsure - the case is ambiguous/there is not enough information to decide.
NED2
Entity disambiguation (via description)
gpt-5-mini-2025-08-07
Target entity: MIPS IV Target entity description: MIPS IV is a 64-bit RISC instruction set architecture in the MIPS family, designed to enhance performance and support advanced computing features over its predecessors.
-
A.
MIPS III
MIPS III is a 64-bit RISC instruction set architecture in the MIPS family, extending earlier versions with larger address space and enhanced computational capabilities.
-
B.
MIPS II
MIPS II is the second-generation version of the MIPS instruction set architecture, extending the original design with additional instructions and features for improved performance and functionality.
-
C.
MIPS R4600
The MIPS R4600 is a 64-bit RISC microprocessor from the MIPS family, widely used in mid-1990s workstations and embedded systems for its balance of performance and cost.
-
D.
MIPS R5000
The MIPS R5000 is a 64-bit RISC microprocessor from the MIPS family, widely used in mid-1990s workstations and embedded systems for its balance of performance and cost.
-
E.
MIPS
MIPS is a RISC (Reduced Instruction Set Computer) processor architecture widely used in embedded systems, networking equipment, and academic settings.
- F. None of above. chosen
Statements (48)
| Predicate | Object |
|---|---|
| instanceOf |
MIPS architecture revision
ⓘ
instruction set architecture ⓘ |
| architectureFamily | MIPS NERFINISHED ⓘ |
| backwardCompatibleWith |
MIPS I
NERFINISHED
ⓘ
MIPS II NERFINISHED ⓘ MIPS III NERFINISHED ⓘ |
| bitWidth | 64-bit ⓘ |
| category |
64-bit ISA
ⓘ
RISC ISA ⓘ |
| designer | MIPS Technologies NERFINISHED ⓘ |
| designGoal |
higher performance than MIPS III
ⓘ
improved floating-point performance ⓘ improved support for 64-bit computing ⓘ support for advanced compiler optimizations ⓘ |
| instructionSetType | RISC ⓘ |
| introducedFeature |
conditional move (MOVN/MOVZ) for integers
ⓘ
enhanced floating-point compare and branch support ⓘ floating-point conditional move (C.cond.fmt + MOVT/MOVF style) ⓘ prefetch (PREF) instruction ⓘ trap-on-condition (TEQ, TNE, TGE, TLT variants) refinements ⓘ |
| pipelineModel | load/store architecture ⓘ |
| predecessor | MIPS III NERFINISHED ⓘ |
| registerCount |
32 floating-point registers
ⓘ
32 general-purpose integer registers ⓘ |
| standardizedBy | MIPS Technologies architecture manuals ⓘ |
| successor | MIPS V NERFINISHED ⓘ |
| supports |
32-bit integer operations
ⓘ
64-bit general-purpose registers ⓘ 64-bit integer operations ⓘ 64-bit load and store instructions ⓘ 64-bit virtual address space (implementation-dependent limits) ⓘ IEEE 754 floating-point NERFINISHED ⓘ big-endian implementations ⓘ conditional move instructions ⓘ double-precision floating-point ⓘ enhanced floating-point compare instructions ⓘ floating-point conditional move ⓘ fused multiply-add style operations (via paired instructions) ⓘ improved branch instructions ⓘ little-endian implementations ⓘ prefetch instructions ⓘ single-precision floating-point ⓘ trap-on-condition instructions ⓘ |
| usedIn |
MIPS R10000
NERFINISHED
ⓘ
MIPS R12000 NERFINISHED ⓘ MIPS R14000 NERFINISHED ⓘ SGI high-end workstations ⓘ SGI servers ⓘ |
How these facts were elicited
The pipeline generated the facts above by prompting gpt-5.1 with this entity's name + description and the instruction below.
Instruction
You are a knowledge base construction expert. Given a subject entity and a description of it, return factual statements that you know for the subject as a JSON list of dictionaries(triples), where keys must be "subject", "predicate" and "object". The number of facts may be very high, between 25 to 50 or more, for very popular subjects. For less popular subjects, the number of facts can be very low, like 5 or 10. # Requirements - If you don't know the subject at all, return an empty list. - If the subject is not a named entity, return an empty list. - Include at least one triple where predicate is "instanceOf". - Do not get too wordy. - Separate several objects into multiple triples with one object.
Input
Subject: MIPS IV Description of subject: MIPS IV is a 64-bit RISC instruction set architecture in the MIPS family, designed to enhance performance and support advanced computing features over its predecessors.
Referenced by (1)
Full triples — surface form annotated when it differs from this entity's canonical label.