SH-2

E724209

SH-2 is a 32-bit member of the SuperH family of RISC microprocessor cores, used in embedded systems for efficient, low-power computing.

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Statements (47)

Predicate Object
instanceOf 32-bit RISC architecture
SuperH family member
microprocessor core
addressSpace 32-bit address space
architectureFamily SuperH NERFINISHED
bitWidth 32-bit
compatibleWith SuperH instruction set NERFINISHED
designedFor embedded systems
designGoal efficient embedded computing
high code density
low power consumption
developedBy Hitachi NERFINISHED
Renesas Electronics predecessors
hasFeature conditional execution via branches
delay slot branches
on-chip interrupt controller (in many implementations)
on-chip serial interfaces (in many implementations)
on-chip timers (in many implementations)
hasRegisterFile control registers
general-purpose registers
instructionSetArchitecture RISC NERFINISHED
introducedAs second-generation SuperH core
market embedded microcontrollers
performanceCharacteristic high MIPS per watt
powerCharacteristic low-power operation
predecessor SH-1 NERFINISHED
successor SH-3
SH-4
supports Harvard architecture variants
branch and jump instructions
exception handling
fixed-length 16-bit instructions
integer arithmetic operations
interrupt handling
load/store architecture
logical operations
on-chip cache variants
shift and rotate operations
targetApplication embedded controllers
real-time control
usedIn Sega Saturn NERFINISHED
arcade systems
automotive control systems
consumer electronics
game consoles
industrial control systems
wordSize 32-bit

Referenced by (1)

Full triples — surface form annotated when it differs from this entity's canonical label.

SuperH hasVersion SH-2