SH-1
E724208
SH-1 is the first-generation implementation of the SuperH 32-bit RISC microprocessor architecture developed for embedded systems.
Statements (39)
| Predicate | Object |
|---|---|
| instanceOf | microprocessor ⓘ |
| addressSpace | 32-bit ⓘ |
| architectureGeneration | first-generation SuperH ⓘ |
| architectureType | RISC NERFINISHED ⓘ |
| belongsToArchitectureLine | SuperH 32-bit RISC family NERFINISHED ⓘ |
| bitWidth | 32-bit ⓘ |
| codeCompatibility | binary compatible within SuperH family (with constraints) ⓘ |
| CPUArchitectureFamily | SuperH NERFINISHED ⓘ |
| designedBy | Hitachi NERFINISHED ⓘ |
| designedFor | embedded systems ⓘ |
| designGoal |
high performance per clock for embedded tasks
ⓘ
reduced instruction set complexity ⓘ |
| endianSupport | little-endian ⓘ |
| hasFeature |
compact 16-bit instruction encoding for 32-bit core
ⓘ
on-chip peripheral integration (in SoC implementations) ⓘ |
| instructionSetArchitecture | SuperH ISA NERFINISHED ⓘ |
| laterAssociatedWith | Renesas Technology NERFINISHED ⓘ |
| marketSegment |
embedded microcontrollers
ⓘ
embedded microprocessors ⓘ |
| optimizedFor |
code density
ⓘ
low cost ⓘ low power consumption ⓘ |
| pipelineType | simple RISC pipeline ⓘ |
| registerCountType | 32-bit general-purpose registers ⓘ |
| registerFileType | general-purpose registers ⓘ |
| successor | SH-2 ⓘ |
| supports |
conditional branch instructions
ⓘ
integer arithmetic operations ⓘ load-store architecture ⓘ logical operations ⓘ shift and rotate operations ⓘ |
| technologyDomain |
embedded computing
ⓘ
microcontroller-based systems ⓘ |
| typicalUseCase |
automotive control units
ⓘ
consumer electronics ⓘ embedded controllers ⓘ industrial embedded systems ⓘ |
| usesInstructionEncoding | fixed-length 16-bit instructions ⓘ |
| wordLength | 32-bit ⓘ |
Referenced by (1)
Full triples — surface form annotated when it differs from this entity's canonical label.