Questa
E656350
Questa is a hardware design and verification software suite from Mentor Graphics used for simulating and validating complex digital circuits and systems.
Statements (51)
| Predicate | Object |
|---|---|
| instanceOf |
digital circuit simulator
ⓘ
hardware design and verification software suite ⓘ |
| competesWith |
Cadence Xcelium
NERFINISHED
ⓘ
Synopsys VCS NERFINISHED ⓘ |
| developer |
Mentor Graphics
NERFINISHED
ⓘ
Siemens EDA NERFINISHED ⓘ |
| domain |
electronic design automation
ⓘ
semiconductor design ⓘ |
| feature |
assertion-based verification
ⓘ
clock-domain crossing analysis ⓘ code coverage analysis ⓘ constraint random stimulus generation ⓘ coverage-driven verification ⓘ debugging environment for HDL designs ⓘ formal property checking ⓘ functional coverage analysis ⓘ graphical waveform viewer ⓘ integration with verification management tools ⓘ mixed-language simulation ⓘ power-aware simulation ⓘ |
| formerlyKnownAs | ModelSim family extension ⓘ |
| hasComponent |
Questa CDC
NERFINISHED
ⓘ
Questa CoverCheck NERFINISHED ⓘ Questa Formal ⓘ Questa LP NERFINISHED ⓘ Questa Sim NERFINISHED ⓘ Questa Verification IP NERFINISHED ⓘ |
| operatingSystem |
Linux
ⓘ
Windows ⓘ |
| ownedBy | Siemens NERFINISHED ⓘ |
| relatedTo | ModelSim NERFINISHED ⓘ |
| supportsLanguage |
SystemC
NERFINISHED
ⓘ
SystemVerilog NERFINISHED ⓘ VHDL ⓘ Verilog NERFINISHED ⓘ |
| supportsStandard |
OVM
NERFINISHED
ⓘ
SystemVerilog Assertions NERFINISHED ⓘ UVM NERFINISHED ⓘ VHDL-2008 NERFINISHED ⓘ |
| targetUser |
ASIC designers
ⓘ
FPGA designers ⓘ hardware design engineers ⓘ verification engineers ⓘ |
| usedFor |
RTL simulation
ⓘ
formal verification ⓘ functional verification of integrated circuits ⓘ gate-level simulation ⓘ hardware design verification ⓘ low-power verification ⓘ simulation of digital circuits ⓘ system-level verification ⓘ |
Referenced by (1)
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