P6

E637110

P6 is Intel’s sixth-generation x86 microarchitecture that introduced out-of-order and speculative execution, forming the basis for later Pentium II/III and early Core designs.

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All labels observed (1)

Label Occurrences
P6 canonical 2

Statements (48)

Predicate Object
instanceOf Intel x86 microarchitecture
microarchitecture
architectureFamily x86
basisFor Pentium II NERFINISHED
Pentium II Xeon NERFINISHED
Pentium III NERFINISHED
Pentium III Xeon NERFINISHED
Pentium Pro NERFINISHED
early Intel Core microarchitecture designs
branchPrediction dynamic branch predictor
compatibility IA-32 NERFINISHED
designer Intel NERFINISHED
designGoal higher performance per clock
improved efficiency over P5
executionModel out-of-order
speculative
familyName P6 microarchitecture family NERFINISHED
generation sixth-generation x86
influenced Intel Core microarchitecture NERFINISHED
later x86 microarchitectures
introducedFeature dynamic branch prediction
micro-ops based execution
non-blocking caches
out-of-order execution
register renaming
reorder buffer
reservation stations
speculative execution
speculative retirement of instructions
super-scalar execution
superpipelined design
marketSegment desktop computers
server computers
workstation computers
notableCPUCore P6 core
notableImprovementOverPredecessor better branch prediction
higher instructions per cycle
improved floating-point performance
pipelineType superpipelined
successorTo Intel P5 microarchitecture NERFINISHED
P5
usedIn Pentium II Xeon processors NERFINISHED
Pentium II processors NERFINISHED
Pentium III Xeon processors NERFINISHED
Pentium III processors NERFINISHED
Pentium Pro processors NERFINISHED
vendor Intel NERFINISHED
wordSize 32-bit

Referenced by (2)

Full triples — surface form annotated when it differs from this entity's canonical label.