Triple

T9027098
Position Surface form Disambiguated ID Type / Status
Subject Intel SSE E216074 entity
Predicate alsoKnownAs P39 FINISHED
Object Streaming SIMD Extensions
Streaming SIMD Extensions is an Intel processor instruction set that adds single-instruction, multiple-data (SIMD) capabilities to accelerate multimedia, floating-point, and parallel data processing tasks.
E773937 NE FINISHED

How this triple was built (4 steps)

Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.

NER Named-entity recognition gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: Streaming SIMD Extensions | Statement: [Intel SSE, alsoKnownAs, Streaming SIMD Extensions]
NED1 Entity disambiguation (via context triple) gpt-5-mini-2025-08-07
Target entity: Streaming SIMD Extensions
Context triple: [Intel SSE, alsoKnownAs, Streaming SIMD Extensions]
  • A. NEON SIMD
    NEON SIMD is ARM's advanced Single Instruction, Multiple Data (SIMD) instruction set extension designed to accelerate multimedia, signal processing, and other parallelizable workloads on ARM processors.
  • B. MIPS SIMD extensions
    MIPS SIMD extensions are a set of vector-processing instructions for the MIPS architecture designed to accelerate multimedia, signal processing, and other data-parallel workloads.
  • C. V (vector extension)
    V (vector extension) is the RISC-V standard for scalable vector processing, enabling efficient parallel computation on variable-length data vectors.
  • D. P (packed-SIMD extension)
    P (packed-SIMD extension) is a RISC-V instruction set extension that adds packed single-instruction multiple-data operations to accelerate parallel data processing tasks such as signal processing and multimedia workloads.
  • E. Tensor Cores
    Tensor Cores are specialized processing units in NVIDIA GPUs designed to accelerate matrix operations for deep learning and AI workloads.
  • F. None of above. chosen
  • G. Unsure - the case is ambiguous/there is not enough information to decide.
NEDg Description generation gpt-5.1
Instruction
Generate a one-sentence description of the target entity. 
You are given a context triple in the form (subject, predicate, object), where the object is the target entity. 
# Instructions
Use the triple to infer relevant information about the entity. Describe the entity based on what is most defining, well-known. 
Avoid repeating the information from the triple, unless really essential.
# Response Format
Return only the sentence: "Description: [one-sentence description of the target entity]"
Input
Entity: Streaming SIMD Extensions
Triple: [Intel SSE, alsoKnownAs, Streaming SIMD Extensions]
Generated description
Streaming SIMD Extensions is an Intel processor instruction set that adds single-instruction, multiple-data (SIMD) capabilities to accelerate multimedia, floating-point, and parallel data processing tasks.
NED2 Entity disambiguation (via description) gpt-5-mini-2025-08-07
Target entity: Streaming SIMD Extensions
Target entity description: Streaming SIMD Extensions is an Intel processor instruction set that adds single-instruction, multiple-data (SIMD) capabilities to accelerate multimedia, floating-point, and parallel data processing tasks.
  • A. NEON SIMD
    NEON SIMD is ARM's advanced Single Instruction, Multiple Data (SIMD) instruction set extension designed to accelerate multimedia, signal processing, and other parallelizable workloads on ARM processors.
  • B. MIPS SIMD extensions
    MIPS SIMD extensions are a set of vector-processing instructions for the MIPS architecture designed to accelerate multimedia, signal processing, and other data-parallel workloads.
  • C. V (vector extension)
    V (vector extension) is the RISC-V standard for scalable vector processing, enabling efficient parallel computation on variable-length data vectors.
  • D. P (packed-SIMD extension)
    P (packed-SIMD extension) is a RISC-V instruction set extension that adds packed single-instruction multiple-data operations to accelerate parallel data processing tasks such as signal processing and multimedia workloads.
  • E. Tensor Cores
    Tensor Cores are specialized processing units in NVIDIA GPUs designed to accelerate matrix operations for deep learning and AI workloads.
  • F. None of above. chosen

Provenance (5 batches)

The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.

Step Stage Batch ID Status When
creating Elicitation batch_69ca83a5fa88819088144801b4dd7245 completed March 30, 2026, 2:07 p.m.
NER Named-entity recognition batch_69cc6a7eb5b881908ace0c3327f06161 completed April 1, 2026, 12:44 a.m.
NED1 Entity disambiguation (via context triple) batch_69cfdbbf786081908df45b4e615bbba9 completed April 3, 2026, 3:24 p.m.
NEDg Description generation batch_69cfdd3117c881908645b6526537571a completed April 3, 2026, 3:30 p.m.
NED2 Entity disambiguation (via description) batch_69cfe10917188190b0223b14e7a8ed39 completed April 3, 2026, 3:47 p.m.
Created at: March 30, 2026, 7:07 p.m.