Triple
T8284581
| Position | Surface form | Disambiguated ID | Type / Status |
|---|---|---|---|
| Subject | Microprocessor without Interlocked Pipeline Stages |
E193757
|
entity |
| Predicate | hasExtension |
P455
|
FINISHED |
| Object |
MIPS SIMD extensions
MIPS SIMD extensions are a set of vector-processing instructions for the MIPS architecture designed to accelerate multimedia, signal processing, and other data-parallel workloads.
|
E724107
|
NE FINISHED |
How this triple was built (4 steps)
Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.
NER
Named-entity recognition
gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: MIPS SIMD extensions | Statement: [Microprocessor without Interlocked Pipeline Stages, hasExtension, MIPS SIMD extensions]
NED1
Entity disambiguation (via context triple)
gpt-5-mini-2025-08-07
Target entity: MIPS SIMD extensions Context triple: [Microprocessor without Interlocked Pipeline Stages, hasExtension, MIPS SIMD extensions]
-
A.
MIPS
MIPS is a RISC (Reduced Instruction Set Computer) processor architecture widely used in embedded systems, networking equipment, and academic settings.
-
B.
P (packed-SIMD extension)
P (packed-SIMD extension) is a RISC-V instruction set extension that adds packed single-instruction multiple-data operations to accelerate parallel data processing tasks such as signal processing and multimedia workloads.
-
C.
NEON SIMD
NEON SIMD is ARM's advanced Single Instruction, Multiple Data (SIMD) instruction set extension designed to accelerate multimedia, signal processing, and other parallelizable workloads on ARM processors.
-
D.
V (vector extension)
V (vector extension) is the RISC-V standard for scalable vector processing, enabling efficient parallel computation on variable-length data vectors.
-
E.
AltiVec
AltiVec is a vector processing extension for the PowerPC architecture that accelerates multimedia, signal processing, and other parallelizable computations.
- F. None of above. chosen
- G. Unsure - the case is ambiguous/there is not enough information to decide.
NEDg
Description generation
gpt-5.1
Instruction
Generate a one-sentence description of the target entity. You are given a context triple in the form (subject, predicate, object), where the object is the target entity. # Instructions Use the triple to infer relevant information about the entity. Describe the entity based on what is most defining, well-known. Avoid repeating the information from the triple, unless really essential. # Response Format Return only the sentence: "Description: [one-sentence description of the target entity]"
Input
Entity: MIPS SIMD extensions Triple: [Microprocessor without Interlocked Pipeline Stages, hasExtension, MIPS SIMD extensions]
Generated description
MIPS SIMD extensions are a set of vector-processing instructions for the MIPS architecture designed to accelerate multimedia, signal processing, and other data-parallel workloads.
NED2
Entity disambiguation (via description)
gpt-5-mini-2025-08-07
Target entity: MIPS SIMD extensions Target entity description: MIPS SIMD extensions are a set of vector-processing instructions for the MIPS architecture designed to accelerate multimedia, signal processing, and other data-parallel workloads.
-
A.
MIPS
MIPS is a RISC (Reduced Instruction Set Computer) processor architecture widely used in embedded systems, networking equipment, and academic settings.
-
B.
P (packed-SIMD extension)
P (packed-SIMD extension) is a RISC-V instruction set extension that adds packed single-instruction multiple-data operations to accelerate parallel data processing tasks such as signal processing and multimedia workloads.
-
C.
NEON SIMD
NEON SIMD is ARM's advanced Single Instruction, Multiple Data (SIMD) instruction set extension designed to accelerate multimedia, signal processing, and other parallelizable workloads on ARM processors.
-
D.
V (vector extension)
V (vector extension) is the RISC-V standard for scalable vector processing, enabling efficient parallel computation on variable-length data vectors.
-
E.
AltiVec
AltiVec is a vector processing extension for the PowerPC architecture that accelerates multimedia, signal processing, and other parallelizable computations.
- F. None of above. chosen
Provenance (5 batches)
The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.
| Step | Stage | Batch ID | Status | When |
|---|---|---|---|---|
| creating | Elicitation | batch_69ca82e217a48190880695635c44b2ed |
completed | March 30, 2026, 2:04 p.m. |
| NER | Named-entity recognition | batch_69cb7ad0535081908bb234cfc0e32b32 |
completed | March 31, 2026, 7:42 a.m. |
| NED1 | Entity disambiguation (via context triple) | batch_69cd687e64a08190a45a1cf5f5c32291 |
completed | April 1, 2026, 6:48 p.m. |
| NEDg | Description generation | batch_69cd6d55196881909cf5ec925792e09f |
completed | April 1, 2026, 7:09 p.m. |
| NED2 | Entity disambiguation (via description) | batch_69cd7e2bdae08190adc51e904e85695e |
completed | April 1, 2026, 8:21 p.m. |
Created at: March 30, 2026, 5:52 p.m.