Triple

T8284474
Position Surface form Disambiguated ID Type / Status
Subject QEMU RISC-V target E193755 entity
Predicate maintainedBy P86 FINISHED
Object QEMU RISC-V maintainers E193755 NE FINISHED

How this triple was built (2 steps)

Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.

NER Named-entity recognition gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: QEMU RISC-V maintainers | Statement: [QEMU RISC-V target, maintainedBy, QEMU RISC-V maintainers]
NED1 Entity disambiguation (via context triple) gpt-5-mini-2025-08-07 
Target entity: QEMU RISC-V maintainers
Context triple: [QEMU RISC-V target, maintainedBy, QEMU RISC-V maintainers]
  • A. QEMU RISC-V target chosen
    QEMU RISC-V target is an emulation backend in the QEMU virtualization platform that allows users to run and test RISC-V software on non-RISC-V host systems.
  • B. RISC-V
    RISC-V is an open, extensible instruction set architecture (ISA) based on the reduced instruction set computing (RISC) principles, widely used for research, embedded systems, and increasingly general-purpose computing.
  • C. Spike RISC-V ISA simulator
    Spike RISC-V ISA simulator is the official reference software simulator for the RISC-V instruction set architecture, used to validate and test RISC-V implementations.
  • D. RISC-V International
    RISC-V International is the global nonprofit consortium that oversees the development, standardization, and promotion of the open RISC-V instruction set architecture.
  • E. QEMU
    QEMU is an open-source machine emulator and virtualizer that enables running operating systems and programs for one hardware platform on another.
  • F. None of above.
  • G. Unsure - the case is ambiguous/there is not enough information to decide.

Provenance (3 batches)

The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.

Step Stage Batch ID Status When
creating Elicitation batch_69ca82e217a48190880695635c44b2ed completed March 30, 2026, 2:04 p.m.
NER Named-entity recognition batch_69cb7ad0535081908bb234cfc0e32b32 completed March 31, 2026, 7:42 a.m.
NED1 Entity disambiguation (via context triple) batch_69cd687e64a08190a45a1cf5f5c32291 completed April 1, 2026, 6:48 p.m.
Created at: March 30, 2026, 5:52 p.m.