Triple

T8284448
Position Surface form Disambiguated ID Type / Status
Subject QEMU RISC-V target E193755 entity
Predicate supportsCPUModel P31542 FINISHED
Object SiFive U-series CPU models
SiFive U-series CPU models are 64-bit RISC-V processor cores designed by SiFive for high-performance, Linux-capable embedded and SoC applications.
 E457337 NE FINISHED

Provenance (5 batches)

Stage Batch ID Job type Status
creating batch_69ca82e217a48190880695635c44b2ed elicitation completed
NER batch_69cbd11ed22c819082bf036602eaa038 ner completed
NED1 batch_69cd687e64a08190a45a1cf5f5c32291 ned_source_triple completed
NED2 batch_69cd7e2bdae08190adc51e904e85695e ned_description completed
NEDg batch_69cd6d55196881909cf5ec925792e09f nedg completed
Created at: March 30, 2026, 5:52 p.m.