Triple
T8284445
| Position | Surface form | Disambiguated ID | Type / Status |
|---|---|---|---|
| Subject | QEMU RISC-V target |
E193755
|
entity |
| Predicate | supportsBoardModel |
P71981
|
FINISHED |
| Object | sifive_e board |
E724102
|
NE FINISHED |
How this triple was built (2 steps)
Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.
NER
Named-entity recognition
gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: sifive_e board | Statement: [QEMU RISC-V target, supportsBoardModel, sifive_e board]
NED1
Entity disambiguation (via context triple)
gpt-5-mini-2025-08-07
Target entity: sifive_e board Context triple: [QEMU RISC-V target, supportsBoardModel, sifive_e board]
-
A.
sifive_u board
chosen
The sifive_u board is a RISC-V development platform modeled in QEMU, commonly used for running and testing 64-bit RISC-V software in a virtualized environment.
-
B.
SiFive
SiFive is a semiconductor company known for designing customizable RISC‑V processor cores and platforms used in a wide range of computing applications.
-
C.
Lattice ECP5
Lattice ECP5 is a family of low-power, mid-range FPGAs designed for cost-sensitive, high-volume applications such as communications, industrial, and consumer electronics.
-
D.
Nios II
Nios II is a soft-core 32-bit RISC processor architecture developed by Altera (now Intel) for implementation on FPGA devices.
-
E.
RISC-V
RISC-V is an open, extensible instruction set architecture (ISA) based on the reduced instruction set computing (RISC) principles, widely used for research, embedded systems, and increasingly general-purpose computing.
- F. None of above.
- G. Unsure - the case is ambiguous/there is not enough information to decide.
Provenance (3 batches)
The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.
| Step | Stage | Batch ID | Status | When |
|---|---|---|---|---|
| creating | Elicitation | batch_69ca82e217a48190880695635c44b2ed |
completed | March 30, 2026, 2:04 p.m. |
| NER | Named-entity recognition | batch_69cbd11ed22c819082bf036602eaa038 |
completed | March 31, 2026, 1:50 p.m. |
| NED1 | Entity disambiguation (via context triple) | batch_69cd952399dc8190914951d4e9e36c38 |
completed | April 1, 2026, 9:58 p.m. |
Created at: March 30, 2026, 5:52 p.m.