Triple

T8284444
Position Surface form Disambiguated ID Type / Status
Subject QEMU RISC-V target E193755 entity
Predicate supportsBoardModel P71981 FINISHED
Object sifive_u board
The sifive_u board is a RISC-V development platform modeled in QEMU, commonly used for running and testing 64-bit RISC-V software in a virtualized environment.
E724102 NE FINISHED

How this triple was built (4 steps)

Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.

NER Named-entity recognition gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: sifive_u board | Statement: [QEMU RISC-V target, supportsBoardModel, sifive_u board]
NED1 Entity disambiguation (via context triple) gpt-5-mini-2025-08-07
Target entity: sifive_u board
Context triple: [QEMU RISC-V target, supportsBoardModel, sifive_u board]
  • A. SiFive
    SiFive is a semiconductor company known for designing customizable RISC‑V processor cores and platforms used in a wide range of computing applications.
  • B. RISC-V
    RISC-V is an open, extensible instruction set architecture (ISA) based on the reduced instruction set computing (RISC) principles, widely used for research, embedded systems, and increasingly general-purpose computing.
  • C. Calliope mini
    Calliope mini is a small educational microcontroller board designed to teach children and beginners programming and electronics through interactive projects.
  • D. Lattice ECP5
    Lattice ECP5 is a family of low-power, mid-range FPGAs designed for cost-sensitive, high-volume applications such as communications, industrial, and consumer electronics.
  • E. SoC FPGA
    A SoC FPGA is an integrated device that combines a traditional FPGA’s programmable logic with embedded processor cores and peripheral interfaces on a single chip to enable flexible, high-performance system-on-chip designs.
  • F. None of above. chosen
  • G. Unsure - the case is ambiguous/there is not enough information to decide.
NEDg Description generation gpt-5.1
Instruction
Generate a one-sentence description of the target entity. 
You are given a context triple in the form (subject, predicate, object), where the object is the target entity. 
# Instructions
Use the triple to infer relevant information about the entity. Describe the entity based on what is most defining, well-known. 
Avoid repeating the information from the triple, unless really essential.
# Response Format
Return only the sentence: "Description: [one-sentence description of the target entity]"
Input
Entity: sifive_u board
Triple: [QEMU RISC-V target, supportsBoardModel, sifive_u board]
Generated description
The sifive_u board is a RISC-V development platform modeled in QEMU, commonly used for running and testing 64-bit RISC-V software in a virtualized environment.
NED2 Entity disambiguation (via description) gpt-5-mini-2025-08-07
Target entity: sifive_u board
Target entity description: The sifive_u board is a RISC-V development platform modeled in QEMU, commonly used for running and testing 64-bit RISC-V software in a virtualized environment.
  • A. SiFive
    SiFive is a semiconductor company known for designing customizable RISC‑V processor cores and platforms used in a wide range of computing applications.
  • B. RISC-V
    RISC-V is an open, extensible instruction set architecture (ISA) based on the reduced instruction set computing (RISC) principles, widely used for research, embedded systems, and increasingly general-purpose computing.
  • C. Calliope mini
    Calliope mini is a small educational microcontroller board designed to teach children and beginners programming and electronics through interactive projects.
  • D. Lattice ECP5
    Lattice ECP5 is a family of low-power, mid-range FPGAs designed for cost-sensitive, high-volume applications such as communications, industrial, and consumer electronics.
  • E. SoC FPGA
    A SoC FPGA is an integrated device that combines a traditional FPGA’s programmable logic with embedded processor cores and peripheral interfaces on a single chip to enable flexible, high-performance system-on-chip designs.
  • F. None of above. chosen

Provenance (5 batches)

The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.

Step Stage Batch ID Status When
creating Elicitation batch_69ca82e217a48190880695635c44b2ed completed March 30, 2026, 2:04 p.m.
NER Named-entity recognition batch_69cbd11ed22c819082bf036602eaa038 completed March 31, 2026, 1:50 p.m.
NED1 Entity disambiguation (via context triple) batch_69cd687e64a08190a45a1cf5f5c32291 completed April 1, 2026, 6:48 p.m.
NEDg Description generation batch_69cd6d55196881909cf5ec925792e09f completed April 1, 2026, 7:09 p.m.
NED2 Entity disambiguation (via description) batch_69cd7e2bdae08190adc51e904e85695e completed April 1, 2026, 8:21 p.m.
Created at: March 30, 2026, 5:52 p.m.