Triple
T7664739
| Position | Surface form | Disambiguated ID | Type / Status |
|---|---|---|---|
| Subject | MMIX |
E173597
|
entity |
| Predicate | documentedIn |
P309
|
FINISHED |
| Object | MMIXware: A RISC Computer for the Third Millennium |
E173597
|
NE FINISHED |
How this triple was built (2 steps)
Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.
NER
Named-entity recognition
gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: MMIXware: A RISC Computer for the Third Millennium | Statement: [MMIX, documentedIn, MMIXware: A RISC Computer for the Third Millennium]
NED1
Entity disambiguation (via context triple)
gpt-5-mini-2025-08-07
Target entity: MMIXware: A RISC Computer for the Third Millennium Context triple: [MMIX, documentedIn, MMIXware: A RISC Computer for the Third Millennium]
-
A.
The Universal Computer
The Universal Computer is a book by mathematician and logician Martin Davis that traces the history and development of the concept of computation and the universal Turing machine.
-
B.
Computer Architecture: Concepts and Evolution
"Computer Architecture: Concepts and Evolution" is a comprehensive reference book that traces the historical development and fundamental principles of computer architecture, co-authored by Gerrit Blaauw and Frederick Brooks.
-
C.
MMIX
chosen
MMIX is a 64-bit RISC-style hypothetical computer architecture designed by Donald Knuth as the pedagogical machine for later volumes of *The Art of Computer Programming*.
-
D.
Spike RISC-V ISA simulator
Spike RISC-V ISA simulator is the official reference software simulator for the RISC-V instruction set architecture, used to validate and test RISC-V implementations.
-
E.
Xe-HPG microarchitecture
Xe-HPG microarchitecture is Intel’s high-performance gaming-oriented GPU architecture designed to power its discrete Arc graphics cards with advanced features like hardware-accelerated ray tracing.
- F. None of above.
- G. Unsure - the case is ambiguous/there is not enough information to decide.
Provenance (3 batches)
The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.
| Step | Stage | Batch ID | Status | When |
|---|---|---|---|---|
| creating | Elicitation | batch_69c699562484819086752091e3164a27 |
completed | March 27, 2026, 2:51 p.m. |
| NER | Named-entity recognition | batch_69c701bfb67c81908b416802eaf0faac |
completed | March 27, 2026, 10:16 p.m. |
| NED1 | Entity disambiguation (via context triple) | batch_69c89b1fdccc8190a69b4745dc3b2347 |
completed | March 29, 2026, 3:23 a.m. |
Created at: March 27, 2026, 4 p.m.