Triple

T7388431
Position Surface form Disambiguated ID Type / Status
Subject Hexagon DSP E170439 entity
Predicate supports P516 FINISHED
Object Hexagon Vector Extensions
Hexagon Vector Extensions are a set of SIMD/vector instruction set enhancements for Qualcomm’s Hexagon DSP architecture, designed to accelerate parallel data processing and signal-processing workloads.
E170439 NE FINISHED

How this triple was built (4 steps)

Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.

NER Named-entity recognition gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: Hexagon Vector Extensions | Statement: [Hexagon DSP, supports, Hexagon Vector Extensions]
NED1 Entity disambiguation (via context triple) gpt-5-mini-2025-08-07
Target entity: Hexagon Vector Extensions
Context triple: [Hexagon DSP, supports, Hexagon Vector Extensions]
  • A. V (vector extension)
    V (vector extension) is the RISC-V standard for scalable vector processing, enabling efficient parallel computation on variable-length data vectors.
  • B. Hexagon DSP
    Hexagon DSP is Qualcomm’s proprietary digital signal processor architecture designed to efficiently handle complex multimedia, AI, and signal-processing tasks in mobile and embedded devices.
  • C. NEON SIMD
    NEON SIMD is ARM's advanced Single Instruction, Multiple Data (SIMD) instruction set extension designed to accelerate multimedia, signal processing, and other parallelizable workloads on ARM processors.
  • D. P (packed-SIMD extension)
    P (packed-SIMD extension) is a RISC-V instruction set extension that adds packed single-instruction multiple-data operations to accelerate parallel data processing tasks such as signal processing and multimedia workloads.
  • E. Vector Multimedia Extension
    Vector Multimedia Extension is a set of SIMD (single instruction, multiple data) instructions for PowerPC processors designed to accelerate multimedia, signal processing, and vector computations.
  • F. None of above. chosen
  • G. Unsure - the case is ambiguous/there is not enough information to decide.
NEDg Description generation gpt-5.1
Instruction
Generate a one-sentence description of the target entity. 
You are given a context triple in the form (subject, predicate, object), where the object is the target entity. 
# Instructions
Use the triple to infer relevant information about the entity. Describe the entity based on what is most defining, well-known. 
Avoid repeating the information from the triple, unless really essential.
# Response Format
Return only the sentence: "Description: [one-sentence description of the target entity]"
Input
Entity: Hexagon Vector Extensions
Triple: [Hexagon DSP, supports, Hexagon Vector Extensions]
Generated description
Hexagon Vector Extensions are a set of SIMD/vector instruction set enhancements for Qualcomm’s Hexagon DSP architecture, designed to accelerate parallel data processing and signal-processing workloads.
NED2 Entity disambiguation (via description) gpt-5-mini-2025-08-07
Target entity: Hexagon Vector Extensions
Target entity description: Hexagon Vector Extensions are a set of SIMD/vector instruction set enhancements for Qualcomm’s Hexagon DSP architecture, designed to accelerate parallel data processing and signal-processing workloads.
  • A. V (vector extension)
    V (vector extension) is the RISC-V standard for scalable vector processing, enabling efficient parallel computation on variable-length data vectors.
  • B. Hexagon DSP chosen
    Hexagon DSP is Qualcomm’s proprietary digital signal processor architecture designed to efficiently handle complex multimedia, AI, and signal-processing tasks in mobile and embedded devices.
  • C. NEON SIMD
    NEON SIMD is ARM's advanced Single Instruction, Multiple Data (SIMD) instruction set extension designed to accelerate multimedia, signal processing, and other parallelizable workloads on ARM processors.
  • D. P (packed-SIMD extension)
    P (packed-SIMD extension) is a RISC-V instruction set extension that adds packed single-instruction multiple-data operations to accelerate parallel data processing tasks such as signal processing and multimedia workloads.
  • E. Vector Multimedia Extension
    Vector Multimedia Extension is a set of SIMD (single instruction, multiple data) instructions for PowerPC processors designed to accelerate multimedia, signal processing, and vector computations.
  • F. None of above.

Provenance (5 batches)

The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.

Step Stage Batch ID Status When
creating Elicitation batch_69c68a5e2c9081909e713ce866e0060a completed March 27, 2026, 1:47 p.m.
NER Named-entity recognition batch_69c6f1f3f5f48190aabe69ba79cbcb93 completed March 27, 2026, 9:09 p.m.
NED1 Entity disambiguation (via context triple) batch_69c802e56fb48190976612d2a94d6ee5 completed March 28, 2026, 4:33 p.m.
NEDg Description generation batch_69c803707cec8190bb474c959ef93d48 completed March 28, 2026, 4:36 p.m.
NED2 Entity disambiguation (via description) batch_69c803ed9ec4819090a9481954060769 completed March 28, 2026, 4:38 p.m.
Created at: March 27, 2026, 3:09 p.m.