Triple

T7387736
Position Surface form Disambiguated ID Type / Status
Subject FPGA E170422 entity
Predicate majorVendor P22771 FINISHED
Object Intel (Altera) E29768 NE FINISHED

How this triple was built (2 steps)

Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.

NER Named-entity recognition gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: Intel (Altera) | Statement: [FPGA, majorVendor, Intel (Altera)]
NED1 Entity disambiguation (via context triple) gpt-5-mini-2025-08-07
Target entity: Intel (Altera)
Context triple: [FPGA, majorVendor, Intel (Altera)]
  • A. Altera chosen
    Altera is a semiconductor company best known for its programmable logic devices (FPGAs) and related design tools, now operating as a subsidiary of Intel.
  • B. Stratix
    Stratix is a high-performance family of field-programmable gate arrays (FPGAs) designed by Altera (now part of Intel) for demanding digital logic and signal processing applications.
  • C. Lattice Semiconductor
    Lattice Semiconductor is an American technology company that designs and manufactures low-power, programmable logic devices used in a wide range of electronics and embedded systems.
  • D. Xilinx
    Xilinx is a leading semiconductor company best known for its programmable logic devices, particularly FPGAs and related development tools.
  • E. Intersil
    Intersil is an American semiconductor company known for designing and manufacturing analog, mixed-signal, and power management integrated circuits for a wide range of electronic applications.
  • F. None of above.
  • G. Unsure - the case is ambiguous/there is not enough information to decide.

Provenance (3 batches)

The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.

Step Stage Batch ID Status When
creating Elicitation batch_69c68a5e2c9081909e713ce866e0060a completed March 27, 2026, 1:47 p.m.
NER Named-entity recognition batch_69c6f1f3f5f48190aabe69ba79cbcb93 completed March 27, 2026, 9:09 p.m.
NED1 Entity disambiguation (via context triple) batch_69c802e56fb48190976612d2a94d6ee5 completed March 28, 2026, 4:33 p.m.
Created at: March 27, 2026, 3:08 p.m.