Triple
T7279486
| Position | Surface form | Disambiguated ID | Type / Status |
|---|---|---|---|
| Subject | Tiger Lake |
E163110
|
entity |
| Predicate | codename |
P2980
|
FINISHED |
| Object | Tiger Lake |
E163110
|
NE FINISHED |
How this triple was built (2 steps)
Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.
NER
Named-entity recognition
gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: Tiger Lake | Statement: [Tiger Lake, codename, Tiger Lake]
NED1
Entity disambiguation (via context triple)
gpt-5-mini-2025-08-07
Target entity: Tiger Lake Context triple: [Tiger Lake, codename, Tiger Lake]
-
A.
Raptor Lake
Raptor Lake is Intel’s 13th-generation Core microarchitecture for desktop and mobile processors, offering improved performance and efficiency over its Alder Lake predecessor.
-
B.
Alder Lake-N
Alder Lake-N is an Intel processor family for low-power devices that combines efficient Gracemont CPU cores with modern integrated graphics and platform features.
-
C.
Broadwell
Broadwell is a small rural village in Oxfordshire, England, known for its traditional Cotswold stone buildings and historic parish church.
-
D.
Tiger Lake microarchitecture
chosen
Tiger Lake microarchitecture is Intel’s 11th-generation Core CPU design for laptops, featuring improved performance, power efficiency, and integrated Iris Xe graphics on a 10 nm SuperFin process.
-
E.
Intel Lakefield platform
Intel Lakefield is a hybrid CPU platform that combines high-performance and low-power cores in a 3D-stacked package to enable ultra-mobile, energy-efficient devices.
- F. None of above.
- G. Unsure - the case is ambiguous/there is not enough information to decide.
Provenance (3 batches)
The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.
| Step | Stage | Batch ID | Status | When |
|---|---|---|---|---|
| creating | Elicitation | batch_69c6885c5964819085b209701769877f |
completed | March 27, 2026, 1:38 p.m. |
| NER | Named-entity recognition | batch_69c6eb339b1081909f648864e210f98e |
completed | March 27, 2026, 8:40 p.m. |
| NED1 | Entity disambiguation (via context triple) | batch_69c7e532a7f08190a5c0b1167dc0be44 |
completed | March 28, 2026, 2:26 p.m. |
Created at: March 27, 2026, 2:59 p.m.