Triple
T7278975
| Position | Surface form | Disambiguated ID | Type / Status |
|---|---|---|---|
| Subject | Intel AVX |
E163100
|
entity |
| Predicate | introducedInMicroarchitecture |
P74863
|
FINISHED |
| Object |
Intel Sandy Bridge
Intel Sandy Bridge is Intel’s second-generation Core microarchitecture, notable for integrating the CPU and GPU on a single die and introducing major instruction set and performance enhancements over its predecessors.
|
E653448
|
NE FINISHED |
How this triple was built (5 steps)
Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.
NER
Named-entity recognition
gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: Intel Sandy Bridge | Statement: [Intel AVX, introducedInMicroarchitecture, Intel Sandy Bridge]
NED1
Entity disambiguation (via context triple)
gpt-5-mini-2025-08-07
Target entity: Intel Sandy Bridge Context triple: [Intel AVX, introducedInMicroarchitecture, Intel Sandy Bridge]
-
A.
Intel Haswell microarchitecture
The Intel Haswell microarchitecture is a generation of Intel CPU design that introduced significant performance and efficiency improvements over its predecessors, including enhanced vector processing, integrated graphics, and power management features.
-
B.
Intel 7
Intel 7 is Intel’s advanced semiconductor process node used to fabricate modern CPU microarchitectures like Gracemont, offering improved performance and power efficiency over previous generations.
-
C.
Intel Xeon
Intel Xeon is a family of high-performance x86 processors designed by Intel for servers, workstations, and data center applications requiring reliability, scalability, and advanced multi-core processing.
-
D.
Intel processors
Intel processors are a broad line of microprocessors from Intel Corporation that power a wide range of computing devices, from budget PCs to high-performance servers and workstations.
-
E.
Intel Elkhart Lake platform
The Intel Elkhart Lake platform is a family of low-power system-on-chips designed for embedded and IoT applications, featuring Intel’s Tremont CPU microarchitecture and enhanced graphics and security capabilities.
- F. None of above. chosen
- G. Unsure - the case is ambiguous/there is not enough information to decide.
NEDg
Description generation
gpt-5.1
Instruction
Generate a one-sentence description of the target entity. You are given a context triple in the form (subject, predicate, object), where the object is the target entity. # Instructions Use the triple to infer relevant information about the entity. Describe the entity based on what is most defining, well-known. Avoid repeating the information from the triple, unless really essential. # Response Format Return only the sentence: "Description: [one-sentence description of the target entity]"
Input
Entity: Intel Sandy Bridge Triple: [Intel AVX, introducedInMicroarchitecture, Intel Sandy Bridge]
Generated description
Intel Sandy Bridge is Intel’s second-generation Core microarchitecture, notable for integrating the CPU and GPU on a single die and introducing major instruction set and performance enhancements over its predecessors.
NED2
Entity disambiguation (via description)
gpt-5-mini-2025-08-07
Target entity: Intel Sandy Bridge Target entity description: Intel Sandy Bridge is Intel’s second-generation Core microarchitecture, notable for integrating the CPU and GPU on a single die and introducing major instruction set and performance enhancements over its predecessors.
-
A.
Intel Haswell microarchitecture
The Intel Haswell microarchitecture is a generation of Intel CPU design that introduced significant performance and efficiency improvements over its predecessors, including enhanced vector processing, integrated graphics, and power management features.
-
B.
Intel 7
Intel 7 is Intel’s advanced semiconductor process node used to fabricate modern CPU microarchitectures like Gracemont, offering improved performance and power efficiency over previous generations.
-
C.
Intel Xeon
Intel Xeon is a family of high-performance x86 processors designed by Intel for servers, workstations, and data center applications requiring reliability, scalability, and advanced multi-core processing.
-
D.
Intel processors
Intel processors are a broad line of microprocessors from Intel Corporation that power a wide range of computing devices, from budget PCs to high-performance servers and workstations.
-
E.
Intel Elkhart Lake platform
The Intel Elkhart Lake platform is a family of low-power system-on-chips designed for embedded and IoT applications, featuring Intel’s Tremont CPU microarchitecture and enhanced graphics and security capabilities.
- F. None of above. chosen
PD
Predicate disambiguation
gpt-5-mini-2025-08-07
Target predicate: introducedInMicroarchitecture Context triple: [Intel AVX, introducedInMicroarchitecture, Intel Sandy Bridge]
-
A.
cpuCoreMicroarchitecture
Indicates the specific microarchitecture design implemented in a given CPU core.
-
B.
microarchitectureFeature
Indicates a relationship where a specific microarchitecture possesses or supports a particular hardware or design feature.
-
C.
engineIntroduced
Indicates that a particular engine was first introduced or brought into use at a specific time or in a specific context.
-
D.
cpuModel
Indicates the specific processor model associated with a given computing device or system.
-
E.
firstSupportedCPUCore
chosen
Indicates the CPU core that initially provided support or capability for a given feature, process, or entity.
- F. None of above.
Provenance (6 batches)
The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.
| Step | Stage | Batch ID | Status | When |
|---|---|---|---|---|
| creating | Elicitation | batch_69c6885c5964819085b209701769877f |
completed | March 27, 2026, 1:38 p.m. |
| NER | Named-entity recognition | batch_69c6eb8a0b4881908ff27c5a75bd4a95 |
completed | March 27, 2026, 8:41 p.m. |
| NED1 | Entity disambiguation (via context triple) | batch_69c7db3450208190b67e4329a531ad0c |
completed | March 28, 2026, 1:44 p.m. |
| NEDg | Description generation | batch_69c7dc567004819089c6c4b5322f275f |
completed | March 28, 2026, 1:49 p.m. |
| NED2 | Entity disambiguation (via description) | batch_69c7dd18f8d481908bd7ac86e4388ce5 |
completed | March 28, 2026, 1:52 p.m. |
| PD | Predicate disambiguation | batch_69c6e76a84a081908d4184c55b728e48 |
completed | March 27, 2026, 8:24 p.m. |
Created at: March 27, 2026, 2:59 p.m.