Triple
T7278849
| Position | Surface form | Disambiguated ID | Type / Status |
|---|---|---|---|
| Subject | Intel Turbo Boost Technology |
E163098
|
entity |
| Predicate | instanceOf |
P0
|
FINISHED |
| Object | dynamic frequency scaling technology |
C22271
|
CONCEPT FINISHED |
How this triple was built (1 step)
Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.
CD
Concept disambiguation
gpt-5-mini-2025-08-07
Target class: dynamic frequency scaling technology Context triple: [Intel Turbo Boost Technology, instanceOf, dynamic frequency scaling technology]
-
A.
SIMD instruction set extension
A SIMD instruction set extension is a set of processor instructions that enable performing the same operation simultaneously on multiple data elements to accelerate parallelizable computations.
-
B.
proprietary governor
A proprietary governor is a colonial-era official or authority figure granted governing powers over a territory by a private owner or chartered company rather than directly by a sovereign state.
-
C.
InfiniBand technology generation
InfiniBand technology generation represents a specific iteration of the InfiniBand architecture defined by its protocol features, performance capabilities, and compatibility characteristics across hardware and software implementations.
-
D.
dynamic pricing facility
A dynamic pricing facility is a system or component that automatically adjusts prices in real time based on factors such as demand, supply, customer behavior, and market conditions.
-
E.
RISC architecture
A RISC architecture is a computer processor design that uses a small, highly optimized set of simple instructions to achieve high performance through efficient pipelining and parallelism.
- F. None of above. chosen
Provenance (1 batch)
The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.
| Step | Stage | Batch ID | Status | When |
|---|---|---|---|---|
| creating | Elicitation | batch_69c6885c5964819085b209701769877f |
completed | March 27, 2026, 1:38 p.m. |
Created at: March 27, 2026, 2:59 p.m.