Triple
T7086808
| Position | Surface form | Disambiguated ID | Type / Status |
|---|---|---|---|
| Subject | Intel AVX2 |
E165095
|
entity |
| Predicate | firstSupportedBy |
P74448
|
FINISHED |
| Object |
Intel Haswell microarchitecture
The Intel Haswell microarchitecture is a generation of Intel CPU design that introduced significant performance and efficiency improvements over its predecessors, including enhanced vector processing, integrated graphics, and power management features.
|
E640802
|
NE FINISHED |
How this triple was built (5 steps)
Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.
NER
Named-entity recognition
gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: Intel Haswell microarchitecture | Statement: [Intel AVX2, firstSupportedBy, Intel Haswell microarchitecture]
NED1
Entity disambiguation (via context triple)
gpt-5-mini-2025-08-07
Target entity: Intel Haswell microarchitecture Context triple: [Intel AVX2, firstSupportedBy, Intel Haswell microarchitecture]
-
A.
Tiger Lake microarchitecture
Tiger Lake microarchitecture is Intel’s 11th-generation Core CPU design for laptops, featuring improved performance, power efficiency, and integrated Iris Xe graphics on a 10 nm SuperFin process.
-
B.
Broadwell
Broadwell is a small rural village in Oxfordshire, England, known for its traditional Cotswold stone buildings and historic parish church.
-
C.
Apollo Lake platform
The Apollo Lake platform is Intel’s low-power system-on-chip family for entry-level PCs and embedded devices, built around the Goldmont CPU microarchitecture.
-
D.
Intel Atom
Intel Atom is a line of low-power x86 microprocessors designed primarily for energy-efficient laptops, netbooks, and embedded devices.
-
E.
Intel 64
Intel 64 is Intel’s 64-bit architecture extension that enables x86 processors to handle 64-bit computing, including larger memory addressing and enhanced performance for modern applications.
- F. None of above. chosen
- G. Unsure - the case is ambiguous/there is not enough information to decide.
NEDg
Description generation
gpt-5.1
Instruction
Generate a one-sentence description of the target entity. You are given a context triple in the form (subject, predicate, object), where the object is the target entity. # Instructions Use the triple to infer relevant information about the entity. Describe the entity based on what is most defining, well-known. Avoid repeating the information from the triple, unless really essential. # Response Format Return only the sentence: "Description: [one-sentence description of the target entity]"
Input
Entity: Intel Haswell microarchitecture Triple: [Intel AVX2, firstSupportedBy, Intel Haswell microarchitecture]
Generated description
The Intel Haswell microarchitecture is a generation of Intel CPU design that introduced significant performance and efficiency improvements over its predecessors, including enhanced vector processing, integrated graphics, and power management features.
NED2
Entity disambiguation (via description)
gpt-5-mini-2025-08-07
Target entity: Intel Haswell microarchitecture Target entity description: The Intel Haswell microarchitecture is a generation of Intel CPU design that introduced significant performance and efficiency improvements over its predecessors, including enhanced vector processing, integrated graphics, and power management features.
-
A.
Tiger Lake microarchitecture
Tiger Lake microarchitecture is Intel’s 11th-generation Core CPU design for laptops, featuring improved performance, power efficiency, and integrated Iris Xe graphics on a 10 nm SuperFin process.
-
B.
Broadwell
Broadwell is a small rural village in Oxfordshire, England, known for its traditional Cotswold stone buildings and historic parish church.
-
C.
Apollo Lake platform
The Apollo Lake platform is Intel’s low-power system-on-chip family for entry-level PCs and embedded devices, built around the Goldmont CPU microarchitecture.
-
D.
Intel Atom
Intel Atom is a line of low-power x86 microprocessors designed primarily for energy-efficient laptops, netbooks, and embedded devices.
-
E.
Intel 64
Intel 64 is Intel’s 64-bit architecture extension that enables x86 processors to handle 64-bit computing, including larger memory addressing and enhanced performance for modern applications.
- F. None of above. chosen
PD
Predicate disambiguation
gpt-5-mini-2025-08-07
Target predicate: firstSupportedBy Context triple: [Intel AVX2, firstSupportedBy, Intel Haswell microarchitecture]
-
A.
isSupportedBy
Indicates that an entity is upheld, sustained, or enabled by another entity, which provides necessary assistance, resources, or justification.
-
B.
supportedIn
Indicates that one entity is valid, applicable, or functionally enabled within the context, environment, platform, or scope defined by another entity.
-
C.
supportedAs
Indicates that one entity is accepted, recognized, or treated as being in the role, type, or representation of another entity.
-
D.
previouslySupported
Indicates that an entity provided support to another entity at some time in the past, but not necessarily in the present.
-
E.
hasSupported
Indicates that one entity has provided assistance, endorsement, or backing to another entity, either materially, emotionally, or through advocacy.
- F. None of above. chosen
Provenance (7 batches)
The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.
| Step | Stage | Batch ID | Status | When |
|---|---|---|---|---|
| creating | Elicitation | batch_69c6887d98408190912b9580666b0c1d |
completed | March 27, 2026, 1:39 p.m. |
| NER | Named-entity recognition | batch_69c6e513d9b08190a8a8d213c2264ce4 |
completed | March 27, 2026, 8:14 p.m. |
| NED1 | Entity disambiguation (via context triple) | batch_69c79484a644819091fac0e361f77c91 |
completed | March 28, 2026, 8:42 a.m. |
| NEDg | Description generation | batch_69c795cd08e081908c5f1a59e284063a |
completed | March 28, 2026, 8:48 a.m. |
| NED2 | Entity disambiguation (via description) | batch_69c797711c78819098f9ac674728eb3b |
completed | March 28, 2026, 8:55 a.m. |
| PD | Predicate disambiguation | batch_69c6e1c172148190bf290c07bf579d1f |
completed | March 27, 2026, 8 p.m. |
| PDg | Predicate description generation | batch_69c6e24af9ac8190b24eee206ba8be36 |
completed | March 27, 2026, 8:02 p.m. |
Created at: March 27, 2026, 2:41 p.m.